SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The PSM is triggered at any rising edge of ESISTOP(tsm) signal during a normal cycle. Note that a test cycle insertion does not trigger the PSM. Triggering the PSM means, the PSM starts a sequence moving the current-state byte (Q0...Q7) from the PSM state table located in ESI RAM to the PSM next state latch (V2...V6 or V3...V6). All accesses to the PSM state table are done automatically with no CPU intervention.
The current-state and next-state logic are reset while the ESI is disabled. The ESI allow selecting either two signals or three signals for the processing. When the ESI is enabled following scenarios do exist for first processing:
Signals PPUS1 and PPUS2 form a 2-bit offset (ESIV2SEL = 1) and signals PPUS1, PPUS2, and PPUS3 form a 3-bit offset (ESIV2SEL = 0) added to the base address of the PSM State Table to determine the byte loaded to the PSM current-state output latch. For example, when two input signals are chosen (ESIV2SEL = 1) and PPUS2 = 1, and PPUS1 = 0, the byte loaded by the PSM will be at the address <current address of PSM State Table> + 2. The next byte and further subsequent bytes are determined by the next state calculations and are calculated by the PSM based on the state table contents and the values of signals PPUS1 and PPUS2.
The PSM needs two TSM clock cycles to complete the processing of the measurement results from a single TSM sequence.