SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The output pulses consists of four different phases: Pause, Excitation, Stop, and Pause again. A state machine in PPG and PPG_A controls the flow. On PPG_A set SAPH_AXPGCTL.XMOD = 0 for single tone generation. When the PPG or PPG_A is triggered, it leaves the Pause phase and generates excitation pulses followed by stop pulses, then goes to Pause phase again (see Figure 21-3, Figure 21-4 and Figure 21-5). The stop pulses have a 180° phase shift compared to the excitation pulses. The PPG generates up to 127 excitation pulses and up to 15 stop pulses, which are controlled by the SAPHPGC.EPULS and SAPHPGC.SPULS bits, respectively. The pulse polarity is programmable in the SAPHPGC.PPOL bit. The signal polarity for Pause can be programmed to be logical high, logical low, or high impedance through the SAPHPGC.PLEV and SAPHPGC.PHIZ bits.
The PPG can be triggered by writing 1 to the SAPHPPGTRIG.PPGTRIG bit when SAPHPGCTL.TRSEL = 0 (register mode) or by the acquisition sequencer (ASQ) when SAPHPGCTL.TRSEL = 1 (auto mode). To avoid unintended pulse outputs, keep SAPHPGCTL.PPGEN = 0 while updating the PPG registers. After the PPG registers are updated, write 1 to the SAPHPGCTL.PPGEN bit before triggering the PPG. The SAPHPGCTL.PPGEN bit must be set before triggering the PPG. The output channel is determined by the SAPHPGCTL.PPGCHSEL bit when SAPHPGCTL.PGSEL = 0 (register mode) or by the acquisition sequencer (ASQ) when SAPHPGCTL.PGSEL = 1 (auto mode). Another layer of output control is inside the PHY, so both blocks must be configured properly (see Section 21.3). The PPG or PPG_A automatically stops when it completes generating the pulses. To stop generating pulses before completion, regardless of operation mode, write 1 to SAPHPGCTL.STOP. The PPG immediately stops generating pulses. The SAPHPGCTL.STOP bit is automatically cleared to zero.