SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Starting of a TSM sequence depends on the selected trigger. Possible triggers are the control bit ESISTART, the divided ACLK and an or combination of these two triggers (ESISTART or divided ACLK).
If the divided ACLK is chosen, the TSM automatically starts and re-starts periodically based on a divided ACLK start signal selected with the ESIDIV2x bits, the ESIDIV3Ax and ESIDIV3Bx bits when ESITSMRP = 0. For example, if ESIDIV2x, ESIDIV3Ax, and ESIDIV3Bx are configured to 270 ACLK cycles, then the TSM automatically starts every 270 ACLK cycles. When ESITSMRP = 1 the TSM restarts immediately with the ESITSM0 state at the end of the previous sequence i.e. with the next ACLK cycle after encountering a state with ESISTOP = 1. The ESIIFG2 interrupt flag is set when the TSM starts.
The ESIDIV2x, ESIDIV3Ax, and ESIDIV3Bx bits may be updated anytime during operation. When updated, the current TSM sequence will continue with the old settings until the last state of the sequence completes. The new settings will take affect at the start of the next sequence.
Setting ESISTART bit is another trigger for starting a TSM sequence. The ESISTART bit is set as long as the actual TSM sequence is in progress. As soon as the TSM sequence is completed and ESITSM0 register is again active for idle state configuration the ESISTART bit is automatically cleared. In case ESISTART is the only source for a start trigger (ESITSMTRG = 01) an ACLK synchronization sequence is performed, which may take up to 2.5 ACLK cycles. For all other cases no special synchronization is needed and TSM starts with the appropriate positive ACLK edge.
NOTE
It is important to set the ESISTOP(tsm) bit at least once the control registers ESITSM2 to ESITSM31. The ESISTOP(tsm) control bit ensures that a user-defined TSM sequence is terminated and the TSM progressing is switching into idle mode awaiting the next start trigger.