SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
The following power states are supported by the UUPS module.
Power State | State Register (UUPSCTL.UPSTATE) | Description |
---|---|---|
OFF | 0 | The USS module is fully powered off. |
TRANSITION | 2 | In transition. A new trigger to the PSQ is ignored. |
READY | 3 | The USS module is fully powered up. |
STANDBY | 1 | The USS module is powered off, but SREF is enable for fast wakeup. |
TIMEOUT | 0 | The USS power-up sequence has not been properly ended. The USS module goes back to OFF state and UUPSRIS.PTMOUT is set to 1.
Note: A time-out should not happen during normal operating conditions. Make sure that the USSXT oscillator is enabled and working properly. |
Figure 19-3 shows the USS module power states and their relationships to each other.
Table 19-2 lists the signals that cause UUPS power state transitions.
Current Power State | Next State | UUPSCTL.UPSTATE | Trigger Signal |
---|---|---|---|
OFF | READY | 0 → 2 → 3 | USS_PWREQ = 0 → 1 |
READY | STANDBY | 3 → 2 → 1 | ASQ_STDBYREQ = 0 → 1 (generated by ASQ) |
READY | OFF | 3 → 2 → 0 | ASQ_PDREQ = 0 → 1 (generated by ASQ) |
READY | OFF | 3 → 2 → 0 | UUPSCTL.USSPWRDN = 0 → 1 |
STANDBY | OFF | 1 → 2 → 0 | UUPSCTL.USSPWRDN = 0 → 1 |
STANDBY | READY | 1 → 2 → 3 | USS_PWRREQ = 0 → 1 |
The USS power state and the device power mode have a relationship as listed in Table 19-3. When the USS module is in READY state, keep the device in LPM0 or AM mode, because the USS module uses resources from the core domain of the device. If the device is in other low-power modes, the measurement performance degrades significantly.
The transition from STANDBY to READY can be extended by a user selectable holdoff delay. This method is used in ultra low bias mode to suppress the PLL operation while the system is still settling. Depending on the transducers and other external circuits some considerable power savings can be achieved.
USS Power State Change | Device Power Mode |
---|---|
READY | LPM0 or higher |
STANDBY | LPM3 or higher (PMMREGOFF = 0) |