SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Watchdog Timer Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WDTPW | |||||||
rw | rw | rw | rw | rw | rw | rw | rw |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTHOLD | WDTSSEL | WDTTMSEL | WDTCNTCL | WDTIS | |||
rw-0 | rw-0 | rw-0 | rw-0 | r0(w) | rw-1 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | WDTPW | RW | 69h |
Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC is generated. |
7 | WDTHOLD | RW | 0h |
Watchdog timer hold. This bit stops the watchdog timer. Setting WDTHOLD = 1 when the WDT is not in use conserves power. 0b = Watchdog timer is not stopped 1b = Watchdog timer is stopped |
6-5 | WDTSSEL | RW | 0h |
Watchdog timer clock source select 00b = SMCLK 01b = ACLK 10b = VLOCLK 11b = X_CLK, same as VLOCLK if not defined differently in data sheet |
4 | WDTTMSEL | RW | 0h |
Watchdog timer mode select 0b = Watchdog mode 1b = Interval timer mode |
3 | WDTCNTCL | RW | 0h |
Watchdog timer counter clear. Setting WDTCNTCL = 1 clears the count value to 0000h. WDTCNTCL is automatically reset. 0b = No action 1b = WDTCNT = 0000h |
2-0 | WDTIS | RW | 4h |
Watchdog timer interval select. These bits select the watchdog timer interval to set the WDTIFG flag or generate a PUC. 000b = Watchdog clock source / 231 (18:12:16 at 32.768 kHz) 001b = Watchdog clock source / 227 (01:08:16 at 32.768 kHz) 010b = Watchdog clock source / 223 (00:04:16 at 32.768 kHz) 011b = Watchdog clock source / 219 (00:00:16 at 32.768 kHz) 100b = Watchdog clock source / 215 (1 s at 32.768 kHz) 101b = Watchdog clock source / 213 (250 ms at 32.768 kHz) 110b = Watchdog clock source / 29 (15.625 ms at 32.768 kHz) 111b = Watchdog clock source / 26 (1.95 ms at 32.768 kHz) |