| 15 |
DONE |
W |
0x0 |
Configuration Done. This bit reads as a zero. The application must write a one to this bit to terminate the PHYHOLD mode set in the EMACPC register and wake up the EPHY.
0x0 = Configuration process is not complete.
0x1 = Configuration process is complete, and the PHY can continue and complete its internal reset sequence.
|
| 14-9 |
RESERVED |
R |
0x0 |
|
| 8 |
TDRAR |
R/W |
0x0 |
TDR Auto-Run at Link Down.
0x0 = Disable automatic execution of TDR.
0x1 = Enable execution of TDR procedure after link down event.
|
| 7 |
LLR |
R/W |
0x0 |
Link Loss Recovery.
0x0 = Normal link loss operation. Link status goes down approximately 250 µs from signal loss.
0x1 = Enable link loss recovery mechanism. This mode allows recovery from short interference and continues to hold the link up for a period of an additional few microseconds until the short interference is gone and the signal is OK.
|
| 6 |
FAMDIX |
R/W |
0x0 |
Fast Auto MDI/MDIX. If both link partners are configured to work in Force 100Base-TX mode (auto-negotiation is disabled), this mode enables automatic MDI/MDIX resolution in a short time.
0x0 = Normal Auto MDI/MDIX mode.
0x1 = Enable Fast Auto MDI/MDIX mode.
|
| 5 |
RAMDIX |
R/W |
0x0 |
Robust Auto MDI/MDIX. If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force 100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock.
0x0 = Normal Auto MDI/MDIX mode.
0x1 = Enable Robust Auto MDI/MDIX resolution.
|
| 4 |
FASTANEN |
R/W |
0x0 |
Fast Auto Negotiation Enable. Adjusting these bits reduces the time it takes to auto-negotiate between two PHYs. When using this option care must be taken to maintain proper operation of the system. While shortening these timer intervals may not cause problems in normal operation, there are certain situations where this may lead to problems.
0x0 = Disable fast auto-negotiation mode. The PHY auto-negotiates using the normal timer setting
0x1 = Enable fast auto-negotiation mode. The PHY auto-negotiates using the timer setting according to the FANSEL bits (bits [3:2] of this register)
|
| 3-2 |
FANSEL |
R/W |
0x0 |
Fast Auto-Negotiation Select Configuration. This bit is preconfigured at reset by the EMACPC register. For custom configuration see . Adjusting these bits reduces the time it takes to auto-negotiate between two PHYs. In Fast AN mode, both PHYs should be configured to the same configuration. These two bits define the duration for each state of the auto-negotiation process according to the table above. The new duration time must be enabled by setting bit 4 (FASTANEN) of this register. Using this mode in cases where both link partners are not configured to the same fast auto-negotiation configuration might produce scenarios with unexpected behavior.
0x0 = Break Link Timer: 80 ms, Link Fail Inhibit Timer: 50 ms, Auto-Negate Wait Timer: 35 ms
0x1 = Break Link Timer: 120 ms, Link Fail Inhibit Timer: 75 ms, Auto-Negate Wait Timer: 50 ms
0x2 = Break Link Timer: 240 ms, Link Fail Inhibit Timer: 150 ms, Auto-Negate Wait Timer: 100 ms
0x3 = Reserved
|
| 1 |
FRXDVDET |
R/W |
0x0 |
FAST RXDV Detection. Enabling this feature allows the PHY to pass data to the MII interface earlier. This bit is set to disabled if using the EMACPC register bits to program the PHY configuration.
0x0 = Disable fast RXDV detection. The PHY operates in normal mode where an internally asserted RXDV signal is sent to the MII interface after detection of /J/K/.
0x1 = An internal RXDV signal is asserted high on receive packet due to detection of /J/ symbol only. Fast RXDV detection allows the PHY to pass data to the MII interface earlier. If a consecutive /K/ does not appear, RXERR is generated.
|
| 0 |
RESERVED |
R |
0x0 |
|