SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 15-99 lists the memory-mapped registers for the EPHY. All register offset addresses not listed in Table 15-99 should be considered as reserved locations and the register contents should not be modified.
PHY registers are accessed through the EMACMIIADDR register thus the base address is not applicable.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers. All addresses given are absolute and are written directly to the MII field of the Ethernet MAC MII Address (EMACMIIADDR) register. The PLA value of the EMACMIIADDR register for the internal PHY is 0x00.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | EPHYBMCR | Ethernet PHY Basic Mode Control - MR0 | Section 15.7.1 |
| 0x1 | EPHYBMSR | Ethernet PHY Basic Mode Status - MR1 | Section 15.7.2 |
| 0x2 | EPHYID1 | Ethernet PHY Identifier Register 1 - MR2 | Section 15.7.3 |
| 0x3 | EPHYID2 | Ethernet PHY Identifier Register 2 - MR3 | Section 15.7.4 |
| 0x4 | EPHYANA | Ethernet PHY Auto-Negotiation Advertisement - MR4 | Section 15.7.5 |
| 0x5 | EPHYANLPA | Ethernet PHY Auto-Negotiation Link Partner Ability -MR5 | Section 15.7.6 |
| 0x6 | EPHYANER | Ethernet PHY Auto-Negotiation Expansion - MR6 | Section 15.7.7 |
| 0x7 | EPHYANNPTR | Ethernet PHY Auto-Negotiation Next Page TX - MR7 | Section 15.7.8 |
| 0x8 | EPHYANLNPTR | Ethernet PHY Auto-Negotiation Link Partner Ability Next Page - MR8 | Section 15.7.9 |
| 0x9 | EPHYCFG1 | Ethernet PHY Configuration 1 - MR9 | Section 15.7.10 |
| 0xA | EPHYCFG2 | Ethernet PHY Configuration 2 - MR10 | Section 15.7.11 |
| 0xB | EPHYCFG3 | Ethernet PHY Configuration 3 - MR11 | Section 15.7.12 |
| 0xD | EPHYREGCTL | Ethernet PHY Register Control - MR13 | Section 15.7.13 |
| 0xE | EPHYADDAR | Ethernet PHY Address or Data - MR14 | Section 15.7.14 |
| 0x10 | EPHYSTS | Ethernet PHY Status - MR16 | Section 15.7.15 |
| 0x11 | EPHYSCR | Ethernet PHY Specific Control - MR17 | Section 15.7.16 |
| 0x12 | EPHYMISR1 | Ethernet PHY MII Interrupt Status 1 - MR18 | Section 15.7.17 |
| 0x13 | EPHYMISR2 | Ethernet PHY MII Interrupt Status 2 - MR19 | Section 15.7.18 |
| 0x14 | EPHYFCSCR | Ethernet PHY False Carrier Sense Counter - MR20 | Section 15.7.19 |
| 0x15 | EPHYRXERCNT | Ethernet PHY Receive Error Count - MR21 | Section 15.7.20 |
| 0x16 | EPHYBISTCR | Ethernet PHY BIST Control - MR22 | Section 15.7.21 |
| 0x18 | EPHYLEDCR | Ethernet PHY LED Control - MR24 | Section 15.7.22 |
| 0x19 | EPHYCTL | Ethernet PHY Control - MR25 | Section 15.7.23 |
| 0x1A | EPHY10BTSC | Ethernet PHY 10Base-T Status/Control - MR26 | Section 15.7.24 |
| 0x1B | EPHYBICSR1 | Ethernet PHY BIST Control and Status 1 - MR27 | Section 15.7.25 |
| 0x1C | EPHYBICSR2 | Ethernet PHY BIST Control and Status 2 - MR28 | Section 15.7.26 |
| 0x1E | EPHYCDCR | Ethernet PHY Cable Diagnostic Control - MR30 | Section 15.7.27 |
| 0x1F | EPHYRCR | Ethernet PHY Reset Control - MR31 | Section 15.7.28 |
| 0x25 | EPHYLEDCFG | Ethernet PHY LED Configuration - MR37 | Section 15.7.29 |
Complex bit access types are encoded to fit into small table cells. Table 15-100 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |