SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Hibernation Clock Control (HIBCC)
This register enables alternate clock sources.
NOTE
This register is in the system clock domain. Writes to this register do not require waiting for the WRC bit of the HIBCTL register to be set.
HIBCC is shown in Figure 6-35 and described in Table 6-30.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYSCLKEN | ||||||
R-0x0 | R/W-0x0 | ||||||