SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
QSSI Clock Configuration (SSICC), offset 0xFC8
The SSICC register controls the baud clock source for the QSSI module.
NOTE
If ALTCLK is used for the QSSI baud clock, the system clock frequency must be at least twice that of the ALTCLK programmed value in Run mode.
SSICC is shown in Figure 23-21 and described in Table 23-17.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CS | ||||||||||||||||||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||