SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 23-4 lists the memory-mapped registers for the QSSI. All register offset addresses not listed in Table 23-4 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the base address of each QSSI module:
The QSSI module clock must be enabled before the registers can be programmed (see Section 4.2.92). The Rn bit of the PRSSI register must be read as 0x1 before any QSSI module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | SSICR0 | QSSI Control 0 | Section 23.5.1 |
| 0x4 | SSICR1 | QSSI Control 1 | Section 23.5.2 |
| 0x8 | SSIDR | QSSI Data | Section 23.5.3 |
| 0xC | SSISR | QSSI Status | Section 23.5.4 |
| 0x10 | SSICPSR | QSSI Clock Prescale | Section 23.5.5 |
| 0x14 | SSIIM | QSSI Interrupt Mask | Section 23.5.6 |
| 0x18 | SSIRIS | QSSI Raw Interrupt Status | Section 23.5.7 |
| 0x1C | SSIMIS | QSSI Masked Interrupt Status | Section 23.5.8 |
| 0x20 | SSIICR | QSSI Interrupt Clear | Section 23.5.9 |
| 0x24 | SSIDMACTL | QSSI DMA Control | Section 23.5.10 |
| 0xFC0 | SSIPP | QSSI Peripheral Properties | Section 23.5.11 |
| 0xFC8 | SSICC | QSSI Clock Configuration | Section 23.5.12 |
| 0xFD0 | SSIPeriphID4 | QSSI Peripheral Identification 4 | Section 23.5.13 |
| 0xFD4 | SSIPeriphID5 | QSSI Peripheral Identification 5 | Section 23.5.14 |
| 0xFD8 | SSIPeriphID6 | QSSI Peripheral Identification 6 | Section 23.5.15 |
| 0xFDC | SSIPeriphID7 | QSSI Peripheral Identification 7 | Section 23.5.16 |
| 0xFE0 | SSIPeriphID0 | QSSI Peripheral Identification 0 | Section 23.5.17 |
| 0xFE4 | SSIPeriphID1 | QSSI Peripheral Identification 1 | Section 23.5.18 |
| 0xFE8 | SSIPeriphID2 | QSSI Peripheral Identification 2 | Section 23.5.19 |
| 0xFEC | SSIPeriphID3 | QSSI Peripheral Identification 3 | Section 23.5.20 |
| 0xFF0 | SSIPCellID0 | QSSI PrimeCell Identification 0 | Section 23.5.21 |
| 0xFF4 | SSIPCellID1 | QSSI PrimeCell Identification 1 | Section 23.5.22 |
| 0xFF8 | SSIPCellID2 | QSSI PrimeCell Identification 2 | Section 23.5.23 |
| 0xFFC | SSIPCellID3 | QSSI PrimeCell Identification 3 | Section 23.5.24 |
Complex bit access types are encoded to fit into small table cells. Table 23-5 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1CW | 1 to clearWrite |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |