| 31-7 |
RESERVED |
R |
0x0 |
|
| 6 |
EOTMIS |
R |
0x0 |
End of Transmit Masked Interrupt Status. This bit is cleared when a 1 is written to the EOTIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the transmission of the last data bit.
|
| 5 |
DMATXMIS |
R |
0x0 |
QSSI Transmit DMA Masked Interrupt Status. This bit is cleared when a 1 is written to the DMATXIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the completion of the transmit DMA.
|
| 4 |
DMARXMIS |
R |
0x0 |
QSSI Receive DMA Masked Interrupt Status. This bit is cleared when a 1 is written to the DMARXIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the completion of the receive DMA.
|
| 3 |
TXMIS |
R |
0x0 |
QSSI Transmit FIFO Masked Interrupt Status. This bit is cleared when the transmit FIFO is more than half empty.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the transmit FIFO being half empty or less.
|
| 2 |
RXMIS |
R |
0x0 |
QSSI Receive FIFO Masked Interrupt Status. This bit is cleared when the receive FIFO is less than half full.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the receive FIFO being half full or more.
|
| 1 |
RTMIS |
R |
0x0 |
QSSI Receive Time-Out Masked Interrupt Status. This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the receive time out.
|
| 0 |
RORMIS |
R |
0x0 |
QSSI Receive Overrun Masked Interrupt Status. This bit is cleared when a 1 is written to the RORIC bit in the SSI Interrupt Clear (SSIICR) register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the receive FIFO overflowing.
|