26.5.7 UARTLCRH Register (Offset = 0x2C) [reset = 0x0]
UART Line Control (UARTLCRH)
The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.
UARTLCRH is shown in Figure 26-10 and described in Table 26-10.
Return to Summary Table.
Figure 26-10 UARTLCRH Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| SPS |
WLEN |
FEN |
STP2 |
EPS |
PEN |
BRK |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 26-10 UARTLCRH Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
SPS |
R/W |
0x0 |
UART Stick Parity Select.
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0.
When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled. |
| 6-5 |
WLEN |
R/W |
0x0 |
UART Word Length.
The bits indicate the number of data bits transmitted or received in a frame as follows:
0x0 = 5 bits (default)
0x1 = 6 bits
0x2 = 7 bits
0x3 = 8 bits
|
| 4 |
FEN |
R/W |
0x0 |
UART Enable FIFOs.
0x0 = The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
0x1 = The transmit and receive FIFO buffers are enabled (FIFO mode).
|
| 3 |
STP2 |
R/W |
0x0 |
UART Two Stop Bits Select.
0x0 = One stop bit is transmitted at the end of a frame.
0x1 = Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received.When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.
|
| 2 |
EPS |
R/W |
0x0 |
UART Even Parity Select.
This bit has no effect when parity is disabled by the PEN bit.
0x0 = Odd parity is performed, which checks for an odd number of 1s.
0x1 = Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits.
|
| 1 |
PEN |
R/W |
0x0 |
UART Parity Enable.
0x0 = Parity is disabled and no parity bit is added to the data frame.
0x1 = Parity checking and generation is enabled.
|
| 0 |
BRK |
R/W |
0x0 |
UART Send Break.
0x0 = Normal use.
0x1 = A Low level is continually output on the UnTx signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods).
|