SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 26-2 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 26-2 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the base address of each instance of the UART:
The UART module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed.
The UART must be disabled (see the UARTEN bit in the UARTCTL register in Section 26.5.8) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.
NOTE
Registers that contain bits for modem control or status only apply to the following UARTs:
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | UARTDR | UART Data | Section 26.5.1 |
| 0x4 | UARTRSR/UARTECR | UART Receive Status/Error Clear | Section 26.5.2 |
| 0x18 | UARTFR | UART Flag | Section 26.5.3 |
| 0x20 | UARTILPR | UART IrDA Low-Power Register | Section 26.5.4 |
| 0x24 | UARTIBRD | UART Integer Baud-Rate Divisor | Section 26.5.5 |
| 0x28 | UARTFBRD | UART Fractional Baud-Rate Divisor | Section 26.5.6 |
| 0x2C | UARTLCRH | UART Line Control | Section 26.5.7 |
| 0x30 | UARTCTL | UART Control | Section 26.5.8 |
| 0x34 | UARTIFLS | UART Interrupt FIFO Level Select | Section 26.5.9 |
| 0x38 | UARTIM | UART Interrupt Mask | Section 26.5.10 |
| 0x3C | UARTRIS | UART Raw Interrupt Status | Section 26.5.11 |
| 0x40 | UARTMIS | UART Masked Interrupt Status | Section 26.5.12 |
| 0x44 | UARTICR | UART Interrupt Clear | Section 26.5.13 |
| 0x48 | UARTDMACTL | UART DMA Control | Section 26.5.14 |
| 0xA4 | UART9BITADDR | UART 9-Bit Self Address | Section 26.5.15 |
| 0xA8 | UART9BITAMASK | UART 9-Bit Self Address Mask | Section 26.5.16 |
| 0xFC0 | UARTPP | UART Peripheral Properties | Section 26.5.17 |
| 0xFC8 | UARTCC | UART Clock Configuration | Section 26.5.18 |
| 0xFD0 | UARTPeriphID4 | UART Peripheral Identification 4 | Section 26.5.19 |
| 0xFD4 | UARTPeriphID5 | UART Peripheral Identification 5 | Section 26.5.20 |
| 0xFD8 | UARTPeriphID6 | UART Peripheral Identification 6 | Section 26.5.21 |
| 0xFDC | UARTPeriphID7 | UART Peripheral Identification 7 | Section 26.5.22 |
| 0xFE0 | UARTPeriphID0 | UART Peripheral Identification 0 | Section 26.5.23 |
| 0xFE4 | UARTPeriphID1 | UART Peripheral Identification 1 | Section 26.5.24 |
| 0xFE8 | UARTPeriphID2 | UART Peripheral Identification 2 | Section 26.5.25 |
| 0xFEC | UARTPeriphID3 | UART Peripheral Identification 3 | Section 26.5.26 |
| 0xFF0 | UARTPCellID0 | UART PrimeCell Identification 0 | Section 26.5.27 |
| 0xFF4 | UARTPCellID1 | UART PrimeCell Identification 1 | Section 26.5.28 |
| 0xFF8 | UARTPCellID2 | UART PrimeCell Identification 2 | Section 26.5.29 |
| 0xFFC | UARTPCellID3 | UART PrimeCell Identification 3 | Section 26.5.30 |
Complex bit access types are encoded to fit into small table cells. Table 26-3 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |