26.5.2 UARTRSR/UARTECR Register (Offset = 0x4) [reset = 0x0]
UART Receive Status/Error Clear (UARTRSR/UARTECR)
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared on reset.
UARTRSR/UARTECR is shown in Figure 26-5 and described in Table 26-5.
Return to Summary Table.
Figure 26-5 UARTRSR/UARTECR Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
OE |
BE |
PE |
FE |
| R-0x0 |
0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 26-5 UARTRSR/UARTECR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
OE |
|
0x0 |
UART Overrun Error.
This bit is cleared by a write to UARTECR.
The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten.
The CPU must read the data in order to empty the FIFO.
0x0 = No data has been lost due to a FIFO overrun.
0x1 = New data was received when the FIFO was full, resulting in data loss.
|
| 2 |
BE |
R |
0x0 |
UART Break Error.
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO.
The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
0x0 = No break condition has occurred
0x1 = A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
|
| 1 |
PE |
R |
0x0 |
UART Parity Error.
This bit is cleared to 0 by a write to UARTECR.
0x0 = No parity error has occurred
0x1 = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.
|
| 0 |
FE |
R |
0x0 |
UART Framing Error.
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO.
0x0 = No framing error has occurred
0x1 = The received character does not have a valid stop bit (a valid stop bit is 1).
|