| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
DMATXMIS |
R |
0x0 |
Transmit DMA Masked Interrupt Status.
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the completion of the transmit DMA.
|
| 16 |
DMARXMIS |
R |
0x0 |
Receive DMA Masked Interrupt Status.
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the completion of the receive DMA.
|
| 15-13 |
RESERVED |
R |
0x0 |
|
| 12 |
9BITMIS |
R |
0x0 |
9-Bit Mode Masked Interrupt Status.
This bit is cleared by writing a 1 to the 9BITIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a receive address match.
|
| 11 |
EOTMIS |
R |
0x0 |
End of Transmission Masked Interrupt Status.
This bit is cleared by writing a 1 to the EOTIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to the transmission of the last data bit.
|
| 10 |
OEMIS |
R |
0x0 |
UART Overrun Error Masked Interrupt Status.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to an overrun error.
|
| 9 |
BEMIS |
R |
0x0 |
UART Break Error Masked Interrupt Status.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a break error.
|
| 8 |
PEMIS |
R |
0x0 |
UART Parity Error Masked Interrupt Status.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a parity error.
|
| 7 |
FEMIS |
R |
0x0 |
UART Framing Error Masked Interrupt Status.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a framing error.
|
| 6 |
RTMIS |
R |
0x0 |
UART Receive Time-Out Masked Interrupt Status.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS status.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to a receive time out.
|
| 5 |
TXMIS |
R |
0x0 |
UART Transmit Masked Interrupt Status.
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set).
|
| 4 |
RXMIS |
R |
0x0 |
UART Receive Masked Interrupt Status.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to passing through the specified receive FIFO level.
|
| 3 |
DSRMIS |
R |
0x0 |
UART Data Set Ready Modem Masked Interrupt Status.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to Data Set Ready.
|
| 2 |
DCDMIS |
R |
0x0 |
UART Data Carrier Detect Modem Masked Interrupt Status.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to Data Carrier Detect.
|
| 1 |
CTSMIS |
R |
0x0 |
UART Clear to Send Modem Masked Interrupt Status.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to Clear to Send.
|
| 0 |
RIMIS |
R |
0x0 |
UART Ring Indicator Modem Masked Interrupt Status.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked interrupt was signaled due to Ring Indicator.
|