SLAU833A May   2020  – October 2020 ADC12DJ3200

 

  1.   1
  2.   2
  3.   3
  4.   4
    1.     5
    2.     6
    3.     7
  5.   8
    1.     9
      1.      10
    2.     11
  6.   12
  7.   13
    1.     14
    2.     15
      1.      16
    3.     17
  8.   18

7.2 Manual SYNC Operation of the ADC12DJ3200EVM

This section provides details on the manual SYNC operation of the ADC12DJ3200EVM.

  1. In the ADC12DJ3200EVM-CVAL GUI, click on the JESD204B tab as Figure 7-3 shows.
    GUID-A1EF5B2E-2139-4285-B7B6-DB6ABBF5BF50-low.pngFigure 7-3 JESD204B Tab
  2. Implement the following steps (in order):
    • Click on the "JESD Block Enable" to disable it (the green arrow should not be lit).
    • Click on the SFORMAT button (to enable it). The FPGA firmware is using unsigned data and a K value of 4.
    • Click the JSYNC_N Sync _Request button (it should be enabled or ‘lit’).
    • Select “No SYNC Input Signal” from the SYNC Input Selection drop-down menu.
    GUID-0D38DF24-2238-44D4-ABCA-EC1E1A7FAEE6-low.pngFigure 7-4 Setting ADC to use Software SYNC
  3. Click on the “JESD Block Enable" (to enable it). The GUI should look now as shown in Figure 7-5.
    GUID-2CC11C16-747D-4C96-83FD-C03FE57ACBB6-low.pngFigure 7-5 SYNC is now set low Inside the ADC