SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

4.3 DMA Registers

Table 4-8 lists the memory-mapped registers for the DMA registers. All register offset addresses not listed in Table 4-8 should be considered as reserved locations and the register contents should not be modified.

Table 4-8 DMA Registers
OffsetAcronymRegister NameGroupSection
400hFSUB_0Subscriber Port 0Go
404hFSUB_1Subscriber Port 1Go
444hFPUB_1Publisher Port 0Go
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt indexGEN_EVENTGo
1058hIMASKInterrupt maskGEN_EVENTGo
1060hRISRaw interrupt statusGEN_EVENTGo
1068hMISMasked interrupt statusGEN_EVENTGo
1070hISETInterrupt setGEN_EVENTGo
1078hICLRInterrupt clearGEN_EVENTGo
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hDMAPRIODMA Channel Priority Control
Go
1110h + formulaDMATCTL[j]DMA Trigger SelectGo
1200h + formulaDMACTL[j]DMA Channel ControlGo
1204h + formulaDMASA[j]DMA Channel Source AddressGo
1208h + formulaDMADA[j]DMA Channel Destination AddressGo
120Ch + formulaDMASZ[j]DMA Channel SizeGo

Complex bit access types are encoded to fit into small table cells. Table 4-9 shows the codes that are used for access types in this section.

Table 4-9 DMA Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

4.3.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 4-4 and described in Table 4-10.

Return to the Summary Table.

Subscriber port

Figure 4-4 FSUB_0
313029282726252423222120191817161514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 4-10 FSUB_0 Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0CHANIDR/W0h0 = disconnected.
1-255 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
FFh = Consult your device data sheet as the actual allowed maximum may be less than 255.

4.3.2 FSUB_1 (Offset = 404h) [Reset = 00000000h]

FSUB_1 is shown in Figure 4-5 and described in Table 4-11.

Return to the Summary Table.

Subscriber port

Figure 4-5 FSUB_1
313029282726252423222120191817161514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 4-11 FSUB_1 Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0CHANIDR/W0h0 = disconnected.
1-255 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
FFh = Consult your device data sheet as the actual allowed maximum may be less than 255.

4.3.3 FPUB_1 (Offset = 444h) [Reset = 00000000h]

FPUB_1 is shown in Figure 4-6 and described in Table 4-12.

Return to the Summary Table.

Publisher port

Figure 4-6 FPUB_1
313029282726252423222120191817161514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 4-12 FPUB_1 Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0CHANIDR/W0h0 = disconnected.
1-255 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
FFh = Consult your device data sheet as the actual allowed maximum may be less than 255.

4.3.4 PDBGCTL (Offset = 1018h) [Reset = 00000003h]

PDBGCTL is shown in Figure 4-7 and described in Table 4-13.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 4-7 PDBGCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDSOFTFREE
R/W-R/W-1hR/W-1h
Table 4-13 PDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

4.3.5 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 4-8 and described in Table 4-14.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, . . . IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS [RIS] and MIS [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-8 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 4-14 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
01h = DMA Channel 0 size counter reached zero (DMASZ=0).
02h = DMA Channel 1 size counter reached zero (DMASZ=0).
03h = DMA Channel 2 size counter reached zero (DMASZ=0).
04h = DMA Channel 3 size counter reached zero (DMASZ=0).
05h = DMA Channel 4 size counter reached zero (DMASZ=0).
06h = DMA Channel 5 size counter reached zero (DMASZ=0).
07h = DMA Channel 6 size counter reached zero (DMASZ=0).
08h = DMA Channel 7 size counter reached zero (DMASZ=0).
09h = DMA Channel 8 size counter reached zero (DMASZ=0).
0Ah = DMA Channel 9 size counter reached zero (DMASZ=0).
0Bh = DMA Channel 10 size counter reached zero (DMASZ=0).
0Ch = DMA Channel 11 size counter reached zero (DMASZ=0).
0Dh = DMA Channel 12 size counter reached zero (DMASZ=0).
0Eh = DMA Channel 13 size counter reached zero (DMASZ=0).
0Fh = DMA Channel 14 size counter reached zero (DMASZ=0).
10h = DMA Channel 15 size counter reached zero (DMASZ=0).
11h = PRE-IRQ event for DMA Channel 0.
12h = PRE-IRQ event for DMA Channel 1.
13h = PRE-IRQ event for DMA Channel 2.
14h = PRE-IRQ event for DMA Channel 3.
15h = PRE-IRQ event for DMA Channel 4.
16h = PRE-IRQ event for DMA Channel 5.
17h = PRE-IRQ event for DMA Channel 6.
18h = PRE-IRQ event for DMA Channel 7.
19h = DMA address error, SRC address not reachable.
1Ah = DMA data error, SRC data might be corrupted (PAR or ECC error).

4.3.6 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 4-9 and described in Table 4-15.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then the corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX [IIDX], as well as MIS [MIS].

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-9 IMASK
3130292827262524
RESERVEDDATAERRADDRERR
R/W-0hR/W-0hR/W-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 4-15 IMASK Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0h
25DATAERRR/W0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR/W0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R/W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R/W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R/W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R/W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R/W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R/W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R/W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R/W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R/W0hDMA Channel 15 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
14DMACH14R/W0hDMA Channel 14 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
13DMACH13R/W0hDMA Channel 13 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
12DMACH12R/W0hDMA Channel 12 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
11DMACH11R/W0hDMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
10DMACH10R/W0hDMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
9DMACH9R/W0hDMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
8DMACH8R/W0hDMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
7DMACH7R/W0hDMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
6DMACH6R/W0hDMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
5DMACH5R/W0hDMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
4DMACH4R/W0hDMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
3DMACH3R/W0hDMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
2DMACH2R/W0hDMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
1DMACH1R/W0hDMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
0DMACH0R/W0hDMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit

4.3.7 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 4-10 and described in Table 4-16.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR [ICLR] register bit even if the corresponding IMASK [IMASK] bit is not enabled.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-10 RIS
3130292827262524
RESERVEDDATAERRADDRERR
R-0hR-0hR-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 4-16 RIS Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25DATAERRR0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred

4.3.8 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 4-11 and described in Table 4-17.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK [IMASK] and RIS [RIS] registers.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-11 MIS
3130292827262524
RESERVEDDATAERRADDRERR
R-0hR-0hR-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 4-17 MIS Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25DATAERRR0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

4.3.9 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 4-12 and described in Table 4-18.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS [RIS] bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS [MIS] bit is also set.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-12 ISET
3130292827262524
RESERVEDDATAERRADDRERR
W-0hW-0hW-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 4-18 ISET Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25DATAERRW0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
10DMACH10W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt

4.3.10 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 4-13 and described in Table 4-19.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-13 ICLR
3130292827262524
RESERVEDDATAERRADDRERR
W-0hW-0hW-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 4-19 ICLR Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25DATAERRW0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
10DMACH10W0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt

4.3.11 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 4-14 and described in Table 4-20.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, . . . IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS [RIS] and MIS [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-14 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 4-20 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
01h = DMA Channel 0 size counter reached zero (DMASZ=0).
02h = DMA Channel 1 size counter reached zero (DMASZ=0).
03h = DMA Channel 2 size counter reached zero (DMASZ=0).
04h = DMA Channel 3 size counter reached zero (DMASZ=0).
05h = DMA Channel 4 size counter reached zero (DMASZ=0).
06h = DMA Channel 5 size counter reached zero (DMASZ=0).
07h = DMA Channel 6 size counter reached zero (DMASZ=0).
08h = DMA Channel 7 size counter reached zero (DMASZ=0).
09h = DMA Channel 8 size counter reached zero (DMASZ=0).
0Ah = DMA Channel 9 size counter reached zero (DMASZ=0).
0Bh = DMA Channel 10 size counter reached zero (DMASZ=0).
0Ch = DMA Channel 11 size counter reached zero (DMASZ=0).
0Dh = DMA Channel 12 size counter reached zero (DMASZ=0).
0Eh = DMA Channel 13 size counter reached zero (DMASZ=0).
0Fh = DMA Channel 14 size counter reached zero (DMASZ=0).
10h = DMA Channel 15 size counter reached zero (DMASZ=0).
11h = PRE-IRQ event for DMA Channel 0.
12h = PRE-IRQ event for DMA Channel 1.
13h = PRE-IRQ event for DMA Channel 2.
14h = PRE-IRQ event for DMA Channel 3.
15h = PRE-IRQ event for DMA Channel 4.
16h = PRE-IRQ event for DMA Channel 5.
17h = PRE-IRQ event for DMA Channel 6.
18h = PRE-IRQ event for DMA Channel 7.
19h = DMA address error, SRC address not reachable.
1Ah = DMA data error, SRC data might be corrupted (PAR or ECC error).

4.3.12 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 4-15 and described in Table 4-21.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then the corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX [IIDX], as well as MIS [MIS].

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-15 IMASK
3130292827262524
RESERVEDDATAERRADDRERR
R/W-0hR/W-0hR/W-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 4-21 IMASK Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0h
25DATAERRR/W0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR/W0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R/W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R/W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R/W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R/W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R/W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R/W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R/W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R/W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R/W0hDMA Channel 15 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
14DMACH14R/W0hDMA Channel 14 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
13DMACH13R/W0hDMA Channel 13 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
12DMACH12R/W0hDMA Channel 12 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
11DMACH11R/W0hDMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
10DMACH10R/W0hDMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
9DMACH9R/W0hDMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
8DMACH8R/W0hDMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
7DMACH7R/W0hDMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
6DMACH6R/W0hDMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
5DMACH5R/W0hDMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
4DMACH4R/W0hDMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
3DMACH3R/W0hDMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
2DMACH2R/W0hDMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
1DMACH1R/W0hDMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
0DMACH0R/W0hDMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit

4.3.13 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 4-16 and described in Table 4-22.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR [ICLR] register bit even if the corresponding IMASK [IMASK] bit is not enabled.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-16 RIS
3130292827262524
RESERVEDDATAERRADDRERR
R-0hR-0hR-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 4-22 RIS Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25DATAERRR0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur
1h = Interrupt occurred

4.3.14 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 4-17 and described in Table 4-23.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK [IMASK] and RIS [RIS] registers.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-17 MIS
3130292827262524
RESERVEDDATAERRADDRERR
R-0hR-0hR-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 4-23 MIS Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25DATAERRR0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRR0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7R0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6R0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5R0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4R0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3R0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2R0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1R0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0R0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15R0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14DMACH14R0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13DMACH13R0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12DMACH12R0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11DMACH11R0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10DMACH10R0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9DMACH9R0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8DMACH8R0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7DMACH7R0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6DMACH6R0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5DMACH5R0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4DMACH4R0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3DMACH3R0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2DMACH2R0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1DMACH1R0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0DMACH0R0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

4.3.15 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 4-18 and described in Table 4-24.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS [RIS] bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS [MIS] bit is also set.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-18 ISET
3130292827262524
RESERVEDDATAERRADDRERR
W-0hW-0hW-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 4-24 ISET Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25DATAERRW0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
10DMACH10W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Set interrupt

4.3.16 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 4-19 and described in Table 4-25.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.

Figure 4-19 ICLR
3130292827262524
RESERVEDDATAERRADDRERR
W-0hW-0hW-0h
2322212019181716
PREIRQCH7PREIRQCH6PREIRQCH5PREIRQCH4PREIRQCH3PREIRQCH2PREIRQCH1PREIRQCH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DMACH15DMACH14DMACH13DMACH12DMACH11DMACH10DMACH9DMACH8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DMACH7DMACH6DMACH5DMACH4DMACH3DMACH2DMACH1DMACH0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 4-25 ICLR Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDW0h
25DATAERRW0hDMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
24ADDRERRW0hDMA address error, SRC address not reachable.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
23PREIRQCH7W0hPre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
22PREIRQCH6W0hPre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
21PREIRQCH5W0hPre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
20PREIRQCH4W0hPre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
19PREIRQCH3W0hPre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
18PREIRQCH2W0hPre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
17PREIRQCH1W0hPre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
16PREIRQCH0W0hPre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit
1h = Set interrupt mask bit
15DMACH15W0hDMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
14DMACH14W0hDMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
13DMACH13W0hDMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
12DMACH12W0hDMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
11DMACH11W0hDMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
10DMACH10W0hDMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
9DMACH9W0hDMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
8DMACH8W0hDMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
7DMACH7W0hDMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
6DMACH6W0hDMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
5DMACH5W0hDMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
4DMACH4W0hDMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
3DMACH3W0hDMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
2DMACH2W0hDMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
1DMACH1W0hDMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt
0DMACH0W0hDMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect
1h = Clear interrupt

4.3.17 EVT_MODE (Offset = 10E0h) [Reset = 00000009h]

EVT_MODE is shown in Figure 4-20 and described in Table 4-26.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 4-20 EVT_MODE
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDEVT1_CFGINT0_CFG
R/W-R-2hR-1h
Table 4-26 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-2EVT1_CFGR2hEvent line mode select for event corresponding to generic event GEN_EVENT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to interrupt event CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

4.3.18 DESC (Offset = 10FCh) [Reset = 2511F000h]

DESC is shown in Figure 4-21 and described in Table 4-27.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 4-21 DESC
31302928272625242322212019181716
MODULEID
R-2511h
1514131211109876543210
FEATUREVERRESERVEDMAJREVMINREV
R-FhR-R-0hR-0h
Table 4-27 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR2511hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERRFhFeature Set for the DMA: number of DMA channel minus one (for example 0->1ch, 2->3ch, 15->16ch).
0h = Smallest value (1 channel)
Fh = Highest value (16 channel)
11-8RESERVEDR0h
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

4.3.19 DMAPRIO (Offset = 1100h) [Reset = 00000000h]

DMAPRIO is shown in Figure 4-22 and described in Table 4-28.

Return to the Summary Table.

DMA Channel Priority Control

Figure 4-22 DMAPRIO
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVEDBURSTSZ
R/W-R/W-0h
15141312111098
RESERVED
R/W-
76543210
RESERVEDROUNDROBIN
R/W-R/W-0h
Table 4-28 DMAPRIO Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0h
17-16BURSTSZR/W0hDefine the burst size of a block transfer, before the priority is re-evaluated
0h = There is no burst size, the whole block transfer is completed on one transfer without interruption
1h = The burst size is 8, after 8 transfers the block transfer is interrupted and the priority is reevaluated
2h = The burst size is 16, after 16 transfers the block transfer is interrupted and the priority is reevaluated
3h = The burst size is 32, after 32 transfers the block transfer is interrupted and the priority is reevaluated
15-1RESERVEDR/W0h
0ROUNDROBINR/W0hRound robin. This bit enables the round-robin DMA channel priorities.
0h = Round robin priority disabled, DMA channel priority is fixed: DMA0-DMA1-DMA2-...-DMA16
1h = Round robin priority enabled, DMA channel priority changes with each transfer

4.3.20 DMATCTL[j] (Offset = 1110h + formula) [Reset = 00000000h]

DMATCTL[j] is shown in Figure 4-23 and described in Table 4-29.

Return to the Summary Table.

DMA Trigger Control

Offset = 1110h + (j * 4h); where j = 0h to Fh

Figure 4-23 DMATCTL[j]
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
DMATINTRESERVEDDMATSEL
R/W-0hR/W-R/W-0h
Table 4-29 DMATCTL[j] Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7DMATINTR/W0hDMA Trigger by Internal Channel
0h = DMATSEL will define external trigger select as transfer trigger.
1h = DMATSEL will define internal channel as transfer trigger select. 0-> Channel0-done, 1-> Channel1-done, ...
6RESERVEDR/W0h
5-0DMATSELR/W0hDMA Trigger Select

Note: Reference the data sheet of the device to see the specific trigger mapping.
00h = Software trigger request
3Fh = Highest possible value

4.3.21 DMACTL[j] (Offset = 1200h + formula) [Reset = 00000000h]

DMACTL[j] is shown in Figure 4-24 and described in Table 4-30.

Return to the Summary Table.

DMA Channel Control

Offset = 1200h + (j * 10h); where j = 0h to Fh

Figure 4-24 DMACTL[j]
3130292827262524
RESERVEDDMATMRESERVEDDMAEM
R/W-R/W-0hR/W-R/W-0h
2322212019181716
DMADSTINCRDMASRCINCR
R/W-0hR/W-0h
15141312111098
RESERVEDDMADSTWDTHRESERVEDDMASRCWDTH
R/W-R/W-0hR/W-R/W-0h
76543210
RESERVEDDMAPREIRQRESERVEDDMAENDMAREQ
R/W-R/W-0hR/W-R/W-0hR/W-0h
Table 4-30 DMACTL[j] Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29-28DMATMR/W0hDMA transfer mode register

Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set.
0h = Single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated and the DMAEN is cleared.
1h = Block transfer. Each trigger transfers the complete block defined in DMASZ. After the transfer is complete an event can be generated and the DMAEN is cleared.
2h = Repeated single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled.
3h = Repeated block transfer. Each trigger transfers the complete block defined in DMASZ. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled.
27-26RESERVEDR/W0h
25-24DMAEMR/W0hDMA extended mode

Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0.
0h = Normal mode is related to transfers from SRC to DST
2h = Fill mode will copy the SA register content as data to DA
3h = Table mode will read an address and data value from SA and write the data to address
23-20DMADSTINCRR/W0hDMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definition in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4.
0h = Address is unchanged (+0)
2h = Decremented by 1 (-1 * DMADSTWDTH)
3h = Incremented by 1 (+1 * DMADSTWDTH)
8h = Stride size 2 (+2 * DMADSTWDTH)
9h = Stride size 3 (+3 * DMADSTWDTH)
Ah = Stride size 4 (+4 * DMADSTWDTH)
Bh = Stride size 5 (+5 * DMADSTWDTH)
Ch = Stride size 6 (+6 * DMADSTWDTH)
Dh = Stride size 7 (+7 * DMADSTWDTH)
Eh = Stride size 8 (+8 * DMADSTWDTH)
Fh = Stride size 9 (+9 * DMADSTWDTH)
19-16DMASRCINCRR/W0hDMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definition in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4.
0h = Address is unchanged (+0)
2h = Decremented by 1 (-1 * DMASRCWDTH)
3h = Incremented by 1 (+1 * DMASRCWDTH)
8h = Stride size 2 (+2 * DMASRCWDTH)
9h = Stride size 3 (+3 * DMASRCWDTH)
Ah = Stride size 4 (+4 * DMASRCWDTH)
Bh = Stride size 5 (+5 * DMASRCWDTH)
Ch = Stride size 6 (+6 * DMASRCWDTH)
Dh = Stride size 7 (+7 * DMASRCWDTH)
Eh = Stride size 8 (+8 * DMASRCWDTH)
Fh = Stride size 9 (+9 * DMASRCWDTH)
15-14RESERVEDR/W0h
13-12DMADSTWDTHR/W0hDMA destination width. This bit selects the destination as a byte, half word, word or long word.
0h = Destination data width is BYTE (8-bit)
1h = Destination data width is HALF-WORD (16-bit)
2h = Destination data width is WORD (32-bit)
3h = Destination data width is LONG-WORD (64-bit)
11-10RESERVEDR/W0h
9-8DMASRCWDTHR/W0hDMA source width. This bit selects the source data width as a byte, half word, word or long word.
0h = Source data width is BYTE (8-bit)
1h = Source data width is HALF-WORD (16-bit)
2h = Source data width is WORD (32-bit)
3h = Source data width is LONG-WORD (64-bit)
7RESERVEDR/W0h
6-4DMAPREIRQR/W0hEnable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete.

Note: This register is only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0.
0h = Pre-IRQ event disabled.
1h = Issue Pre-IRQ event when DMASZ=1
2h = Issue Pre-IRQ event when DMASZ=2
3h = Issue Pre-IRQ event when DMASZ=4
4h = Issue Pre-IRQ event when DMASZ=8
5h = Issue Pre-IRQ event when DMASZ=32
6h = Issue Pre-IRQ event when DMASZ=64
7h = Issue Pre-IRQ event when DMASZ reached the half size point of the original transfer size
3-2RESERVEDR/W0h
1DMAENR/W0hDMA enable
0h = DMA channel disabled
1h = DMA channel enabled
0DMAREQR/W0hDMA request. Software-controlled DMA start. DMAREQ is reset automatically.

0h = Default read value
1h = DMA transfer request (start DMA)

4.3.22 DMASA[j] (Offset = 1204h + formula) [Reset = 00000000h]

DMASA[j] is shown in Figure 4-25 and described in Table 4-31.

Return to the Summary Table.

DMA Channel Source Address

Offset = 1204h + (j * 10h); where j = 0h to Fh

Figure 4-25 DMASA[j]
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 4-31 DMASA[j] Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hDMA Channel Source Address
0h = Smallest value
FFFFFFFFh = Highest possible value

4.3.23 DMADA[j] (Offset = 1208h + formula) [Reset = 00000000h]

DMADA[j] is shown in Figure 4-26 and described in Table 4-32.

Return to the Summary Table.

DMA Channel Destination Address

Offset = 1208h + (j * 10h); where j = 0h to Fh

Figure 4-26 DMADA[j]
313029282726252423222120191817161514131211109876543210
ADDR
R/W-0h
Table 4-32 DMADA[j] Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/W0hDMA Channel Destination Address
0h = Smallest value
FFFFFFFFh = Highest possible value

4.3.24 DMASZ[j] (Offset = 120Ch + formula) [Reset = 00000000h]

DMASZ[j] is shown in Figure 4-27 and described in Table 4-33.

Return to the Summary Table.

DMA Channel Size

Offset = 120Ch + (j * 10h); where j = 0h to Fh

Figure 4-27 DMASZ[j]
313029282726252423222120191817161514131211109876543210
RESERVEDSIZE
R/W-R/W-0h
Table 4-33 DMASZ[j] Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0SIZER/W0hDMA Channel Size in number of transfers
0h = Smallest value
FFFFh = Highest possible value