SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

14.3 DAC12 Registers

Table 14-7 lists the memory-mapped registers for the DAC12 registers. All register offset addresses not listed in Table 14-7 should be considered as reserved locations and the register contents should not be modified.

Table 14-7 DAC12 Registers
Offset Acronym Register Name Group Section
400h FSUB_0 Subscriber Port 0 Go
444h FPUB_1 Publisher port 1 Go
800h PWREN Power enable Go
804h RSTCTL Reset Control Go
814h STAT Status Register Go
1020h IIDX Interrupt index CPU_INT Go
1028h IMASK Interrupt mask CPU_INT Go
1030h RIS Raw interrupt status CPU_INT Go
1038h MIS Masked interrupt status CPU_INT Go
1040h ISET Interrupt set CPU_INT Go
1048h ICLR Interrupt clear CPU_INT Go
1050h IIDX Interrupt index GEN_EVENT Go
1058h IMASK Interrupt mask GEN_EVENT Go
1060h RIS Raw interrupt status GEN_EVENT Go
1068h MIS Masked interrupt status GEN_EVENT Go
1070h ISET Interrupt set GEN_EVENT Go
1078h ICLR Interrupt clear GEN_EVENT Go
10E0h EVT_MODE Event Mode Go
10FCh DESC Module Description Go
1100h CTL0 Control 0 Go
1110h CTL1 Control 1 Go
1120h CTL2 Control 2 Go
1130h CTL3 Control 3 Go
1140h CALCTL Calibration control Go
1160h CALDATA Calibration data Go
1200h DATA0 Data 0 Go

Complex bit access types are encoded to fit into small table cells. Table 14-8 shows the codes that are used for access types in this section.

Table 14-8 DAC12 Access Type Codes
Access Type Code Description
Read Type
R R Read
RH R
H		 Read
Set or cleared by hardware
Write Type
K K Write protected by a key
W W Write
WK W
K		 Write
Write protected by a key
Reset or Default Value
-n Value after reset or the default value

14.3.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 14-8 and described in Table 14-9.

Return to the Summary Table.

Subscriber port 0

Figure 14-8 FSUB_0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CHANID
R/W- R/W-0h
Table 14-9 FSUB_0 Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3-0 CHANID R/W 0h 0 = disconnected.
others = connected to channel_ID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

14.3.2 FPUB_1 (Offset = 444h) [Reset = 00000000h]

FPUB_1 is shown in Figure 14-9 and described in Table 14-10.

Return to the Summary Table.

Publisher port 1

Figure 14-9 FPUB_1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CHANID
R/W- R/W-0h
Table 14-10 FPUB_1 Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3-0 CHANID R/W 0h 0 = disconnected.
others = connected to channel_ID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

14.3.3 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 14-10 and described in Table 14-11.

Return to the Summary Table.

Register to control the power state

Figure 14-10 PWREN
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED ENABLE
R/W- K-0h
Table 14-11 PWREN Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to allow Power State Change
26h = KEY to allow write access to this register
23-1 RESERVED R/W 0h
0 ENABLE K 0h Enable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

14.3.4 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 14-11 and described in Table 14-12.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 14-11 RSTCTL
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-
15 14 13 12 11 10 9 8
RESERVED
W-
7 6 5 4 3 2 1 0
RESERVED RESETSTKYCLR RESETASSERT
W- WK-0h WK-0h
Table 14-12 RSTCTL Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h Unlock key
B1h = KEY to allow write access to this register
23-2 RESERVED W 0h
1 RESETSTKYCLR WK 0h Clear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0 RESETASSERT WK 0h Assert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

14.3.5 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 14-12 and described in Table 14-13.

Return to the Summary Table.

peripheral enable and reset status

Figure 14-12 STAT
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED RESETSTKY
R- R-0h
15 14 13 12 11 10 9 8
RESERVED
R-
7 6 5 4 3 2 1 0
RESERVED
R-
Table 14-13 STAT Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 RESETSTKY R 0h This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0 RESERVED R 0h

14.3.6 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 14-13 and described in Table 14-14.

Return to the Summary Table.

Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.

Figure 14-13 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 14-14 IIDX Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3-0 STAT R 0h Interrupt index status
0h = No pending interrupt
2h = Module ready interrupt
9h = FIFO full interrupt
Ah = FIFO one fourth empty interrupt
Bh = FIFO half empty interrupt
Ch = FIFO three fourth empty interrupt
Dh = FIFO empty interrupt
Eh = FIFO underrun interrupt
Fh = DMA done interrupt

14.3.7 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 14-14 and described in Table 14-15.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS

Figure 14-14 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R/W-0h R/W-0h R/W-0h
Table 14-15 IMASK Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R/W 0h
14 DMADONEIFG R/W 0h Masks DMADONEIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
13 FIFOURUNIFG R/W 0h Masks FIFOURUNIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
12 FIFOEMPTYIFG R/W 0h Masks FIFOEMPTYIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
11 FIFO3B4IFG R/W 0h Masks FIFO3B4IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
10 FIFO1B2IFG R/W 0h Masks FIFO1B2IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
9 FIFO1B4IFG R/W 0h Masks FIFO1B4IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
8 FIFOFULLIFG R/W 0h Masks FIFOFULLIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
7-2 RESERVED R/W 0h
1 MODRDYIFG R/W 0h Masks MODRDYIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
0 RESERVED R/W 0h

14.3.8 RIS (Offset = 1030h) [Reset = 00001E00h]

RIS is shown in Figure 14-15 and described in Table 14-16.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 14-15 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R-0h R-0h R-0h R-1h R-1h R-1h R-1h R-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R-0h R-0h R-0h
Table 14-16 RIS Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14 DMADONEIFG R 0h Raw interrupt status for DMADONEIFG
0h = DMA done condition did not occur
1h = DMA done condition occurred
13 FIFOURUNIFG R 0h Raw interrupt status for FIFOURUNIFG
0h = FIFO underrun condition did not occur
1h = FIFO underrun condition occurred
12 FIFOEMPTYIFG R 1h Raw interrupt status for FIFOEMPTYIFG
0h = FIFO empty condition did not occur
1h = FIFO empty condition occurred
11 FIFO3B4IFG R 1h Raw interrupt status for FIFO3B4IFG
0h = FIFO three fourth empty condition did not occur
1h = FIFO three fourth empty condition occurred
10 FIFO1B2IFG R 1h Raw interrupt status for FIFO1B2IFG
0h = FIFO half empty condition did not occur
1h = FIFO half empty condition occurred
9 FIFO1B4IFG R 1h Raw interrupt status for FIFO1B4IFG
0h = FIFO one fourth empty condition did not occur
1h = FIFO one fourth empty condition occurred
8 FIFOFULLIFG R 0h Raw interrupt status for FIFOFULLIFG
0h = FIFO full condition did not occur
1h = FIFO full condition occurred
7-2 RESERVED R 0h
1 MODRDYIFG R 0h Raw interrupt status for MODRDYIFG
0h = DAC module ready event did not occur
1h = DAC module ready event occurred
0 RESERVED R 0h

14.3.9 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 14-16 and described in Table 14-17.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 14-16 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R-0h R-0h R-0h
Table 14-17 MIS Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14 DMADONEIFG R 0h Masked interrupt status for DMADONEIFG
0h = DMADONEIFG does not request an interrupt service routine
1h = DMADONEIFG requests an interrupt service routine
13 FIFOURUNIFG R 0h Masked interrupt status for FIFOURUNIFG
0h = FIFOURUNIFG does not request an interrupt service routine
1h = FIFOURUNIFG requests an interrupt service routine
12 FIFOEMPTYIFG R 0h Masked interrupt status for FIFOEMPTYIFG
0h = FIFOEMPTYIFG does not request an interrupt service routine
1h = FIFOEMPTYIFG requests an interrupt service routine
11 FIFO3B4IFG R 0h Masked interrupt status for FIFO3B4IFG
0h = FIFO3B4IFG does not request an interrupt service routine
1h = FIFO3B4IFG requests an interrupt service routine
10 FIFO1B2IFG R 0h Masked interrupt status for FIFO1B2IFG
0h = FIFO1B2IFG does not request an interrupt service routine
1h = FIFO1B2IFG requests an interrupt service routine
9 FIFO1B4IFG R 0h Masked interrupt status for FIFO1B4IFG
0h = FIFO1B4IFG does not request an interrupt service routine
1h = FIFO1B4IFG requests an interrupt service routine
8 FIFOFULLIFG R 0h Masked interrupt status for FIFOFULLIFG
0h = FIFOFULLIFG does not request an interrupt service routine
1h = FIFOFULLIFG requests an interrupt service routine
7-2 RESERVED R 0h
1 MODRDYIFG R 0h Masked interrupt status for MODRDYIFG
0h = MODRDYIFG does not request an interrupt service routine
1h = MODRDYIFG requests an interrupt service routine
0 RESERVED R 0h

14.3.10 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 14-17 and described in Table 14-18.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 14-17 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
W-0h W-0h W-0h
Table 14-18 ISET Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED W 0h
14 DMADONEIFG W 0h Sets DMADONEIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to DMADONEIFG is set
13 FIFOURUNIFG W 0h Sets FIFOURUNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOURUNIFG is set
12 FIFOEMPTYIFG W 0h Sets FIFOEMPTYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOEMPTYIFG is set
11 FIFO3B4IFG W 0h Sets FIFO3B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO3B4IFG is set
10 FIFO1B2IFG W 0h Sets FIFO1B2IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B2IFG is set
9 FIFO1B4IFG W 0h Sets FIFO1B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B4IFG is set
8 FIFOFULLIFG W 0h Sets FIFOFULLIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOFULLIFG is set
7-2 RESERVED W 0h
1 MODRDYIFG W 0h Sets MODRDYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to MODRDYIFG is set
0 RESERVED W 0h

14.3.11 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 14-18 and described in Table 14-19.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 14-18 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
W-0h W-0h W-0h
Table 14-19 ICLR Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED W 0h
14 DMADONEIFG W 0h Clears DMADONEIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to DMADONEIFG is cleared
13 FIFOURUNIFG W 0h Clears FIFOURUNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOURUNIFG is cleared
12 FIFOEMPTYIFG W 0h Clears FIFOEMPTYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOEMPTYIFG is cleared
11 FIFO3B4IFG W 0h Clears FIFO3B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO3B4IFG is cleared
10 FIFO1B2IFG W 0h Clears FIFO1B2IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B2IFG is cleared
9 FIFO1B4IFG W 0h Clears FIFO1B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B4IFG is cleared
8 FIFOFULLIFG W 0h Clears FIFOFULLIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOFULLIFG is cleared
7-2 RESERVED W 0h
1 MODRDYIFG W 0h Clears MODRDYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to MODRDYIFG is cleared
0 RESERVED W 0h

14.3.12 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 14-19 and described in Table 14-20.

Return to the Summary Table.

Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.

Figure 14-19 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 14-20 IIDX Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3-0 STAT R 0h Interrupt index status
0h = No pending interrupt
2h = Module ready interrupt
9h = FIFO full interrupt
Ah = FIFO one fourth empty interrupt
Bh = FIFO half empty interrupt
Ch = FIFO three fourth empty interrupt
Dh = FIFO empty interrupt
Eh = FIFO underrun interrupt
Fh = DMA done interrupt

14.3.13 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 14-20 and described in Table 14-21.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS

Figure 14-20 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R/W-0h R/W-0h R/W-0h
Table 14-21 IMASK Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R/W 0h
14 DMADONEIFG R/W 0h Masks DMADONEIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
13 FIFOURUNIFG R/W 0h Masks FIFOURUNIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
12 FIFOEMPTYIFG R/W 0h Masks FIFOEMPTYIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
11 FIFO3B4IFG R/W 0h Masks FIFO3B4IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
10 FIFO1B2IFG R/W 0h Masks FIFO1B2IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
9 FIFO1B4IFG R/W 0h Masks FIFO1B4IFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
8 FIFOFULLIFG R/W 0h Masks FIFOFULLIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
7-2 RESERVED R/W 0h
1 MODRDYIFG R/W 0h Masks MODRDYIFG
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
0 RESERVED R/W 0h

14.3.14 RIS (Offset = 1060h) [Reset = 00001E00h]

RIS is shown in Figure 14-21 and described in Table 14-22.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 14-21 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R-0h R-0h R-0h R-1h R-1h R-1h R-1h R-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R-0h R-0h R-0h
Table 14-22 RIS Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14 DMADONEIFG R 0h Raw interrupt status for DMADONEIFG
0h = DMA done condition did not occur
1h = DMA done condition occurred
13 FIFOURUNIFG R 0h Raw interrupt status for FIFOURUNIFG
0h = FIFO underrun condition did not occur
1h = FIFO underrun condition occurred
12 FIFOEMPTYIFG R 1h Raw interrupt status for FIFOEMPTYIFG
0h = FIFO empty condition did not occur
1h = FIFO empty condition occurred
11 FIFO3B4IFG R 1h Raw interrupt status for FIFO3B4IFG
0h = FIFO three fourth empty condition did not occur
1h = FIFO three fourth empty condition occurred
10 FIFO1B2IFG R 1h Raw interrupt status for FIFO1B2IFG
0h = FIFO half empty condition did not occur
1h = FIFO half empty condition occurred
9 FIFO1B4IFG R 1h Raw interrupt status for FIFO1B4IFG
0h = FIFO one fourth empty condition did not occur
1h = FIFO one fourth empty condition occurred
8 FIFOFULLIFG R 0h Raw interrupt status for FIFOFULLIFG
0h = FIFO full condition did not occur
1h = FIFO full condition occurred
7-2 RESERVED R 0h
1 MODRDYIFG R 0h Raw interrupt status for MODRDYIFG
0h = DAC module ready event did not occur
1h = DAC module ready event occurred
0 RESERVED R 0h

14.3.15 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 14-22 and described in Table 14-23.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 14-22 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
R-0h R-0h R-0h
Table 14-23 MIS Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14 DMADONEIFG R 0h Masked interrupt status for DMADONEIFG
0h = DMADONEIFG does not request an interrupt service routine
1h = DMADONEIFG requests an interrupt service routine
13 FIFOURUNIFG R 0h Masked interrupt status for FIFOURUNIFG
0h = FIFOURUNIFG does not request an interrupt service routine
1h = FIFOURUNIFG requests an interrupt service routine
12 FIFOEMPTYIFG R 0h Masked interrupt status for FIFOEMPTYIFG
0h = FIFOEMPTYIFG does not request an interrupt service routine
1h = FIFOEMPTYIFG requests an interrupt service routine
11 FIFO3B4IFG R 0h Masked interrupt status for FIFO3B4IFG
0h = FIFO3B4IFG does not request an interrupt service routine
1h = FIFO3B4IFG requests an interrupt service routine
10 FIFO1B2IFG R 0h Masked interrupt status for FIFO1B2IFG
0h = FIFO1B2IFG does not request an interrupt service routine
1h = FIFO1B2IFG requests an interrupt service routine
9 FIFO1B4IFG R 0h Masked interrupt status for FIFO1B4IFG
0h = FIFO1B4IFG does not request an interrupt service routine
1h = FIFO1B4IFG requests an interrupt service routine
8 FIFOFULLIFG R 0h Masked interrupt status for FIFOFULLIFG
0h = FIFOFULLIFG does not request an interrupt service routine
1h = FIFOFULLIFG requests an interrupt service routine
7-2 RESERVED R 0h
1 MODRDYIFG R 0h Masked interrupt status for MODRDYIFG
0h = MODRDYIFG does not request an interrupt service routine
1h = MODRDYIFG requests an interrupt service routine
0 RESERVED R 0h

14.3.16 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 14-23 and described in Table 14-24.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 14-23 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
W-0h W-0h W-0h
Table 14-24 ISET Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED W 0h
14 DMADONEIFG W 0h Sets DMADONEIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to DMADONEIFG is set
13 FIFOURUNIFG W 0h Sets FIFOURUNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOURUNIFG is set
12 FIFOEMPTYIFG W 0h Sets FIFOEMPTYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOEMPTYIFG is set
11 FIFO3B4IFG W 0h Sets FIFO3B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO3B4IFG is set
10 FIFO1B2IFG W 0h Sets FIFO1B2IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B2IFG is set
9 FIFO1B4IFG W 0h Sets FIFO1B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B4IFG is set
8 FIFOFULLIFG W 0h Sets FIFOFULLIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOFULLIFG is set
7-2 RESERVED W 0h
1 MODRDYIFG W 0h Sets MODRDYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to MODRDYIFG is set
0 RESERVED W 0h

14.3.17 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 14-24 and described in Table 14-25.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 14-24 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED DMADONEIFG FIFOURUNIFG FIFOEMPTYIFG FIFO3B4IFG FIFO1B2IFG FIFO1B4IFG FIFOFULLIFG
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED MODRDYIFG RESERVED
W-0h W-0h W-0h
Table 14-25 ICLR Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED W 0h
14 DMADONEIFG W 0h Clears DMADONEIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to DMADONEIFG is cleared
13 FIFOURUNIFG W 0h Clears FIFOURUNIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOURUNIFG is cleared
12 FIFOEMPTYIFG W 0h Clears FIFOEMPTYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOEMPTYIFG is cleared
11 FIFO3B4IFG W 0h Clears FIFO3B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO3B4IFG is cleared
10 FIFO1B2IFG W 0h Clears FIFO1B2IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B2IFG is cleared
9 FIFO1B4IFG W 0h Clears FIFO1B4IFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFO1B4IFG is cleared
8 FIFOFULLIFG W 0h Clears FIFOFULLIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to FIFOFULLIFG is cleared
7-2 RESERVED W 0h
1 MODRDYIFG W 0h Clears MODRDYIFG in RIS register
0h = Writing a 0 has no effect
1h = RIS bit corresponding to MODRDYIFG is cleared
0 RESERVED W 0h

14.3.18 EVT_MODE (Offset = 10E0h) [Reset = 00000009h]

EVT_MODE is shown in Figure 14-25 and described in Table 14-26.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 14-25 EVT_MODE
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED EVT1_CFG INT0_CFG
R/W-0h R-2h R-1h
Table 14-26 EVT_MODE Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3-2 EVT1_CFG R 2h Event line mode select for event corresponding to none.GEN_EVENT
0h = The interrupt or event line is disabled.
1h = Event handled by software. Software must clear the associated RIS flag.
2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag.
1-0 INT0_CFG R 1h Event line mode select for event corresponding to none.CPU_INT
0h = The interrupt or event line is disabled.
1h = Event handled by software. Software must clear the associated RIS flag.
2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag.

14.3.19 DESC (Offset = 10FCh) [Reset = 03110000h]

DESC is shown in Figure 14-26 and described in Table 14-27.

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This register identifies the peripheral and its exact version.

Figure 14-26 DESC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODULEID
R-311h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEATUREVER RESERVED MAJREV MINREV
R-0h R- R-0h R-0h
Table 14-27 DESC Field Descriptions
Bit Field Type Reset Description
31-16 MODULEID R 311h Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
15-12 FEATUREVER R 0h Feature Set for the module *instance*
11-8 RESERVED R 0h
7-4 MAJREV R 0h Major rev of the IP
3-0 MINREV R 0h Minor rev of the IP

14.3.20 CTL0 (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 14-27 and described in Table 14-28.

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Control 0 register.

Figure 14-27 CTL0
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED DFM
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED RES
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE
R/W-0h R/W-0h
Table 14-28 CTL0 Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R/W 0h
16 DFM R/W 0h This bit defines the DAC input data format.
0h = Straight binary
1h = Twos complement
15-9 RESERVED R/W 0h
8 RES R/W 0h These bits define the DAC output voltage resolution.
0h = 8-bits resolution
1h = 12-bit resolution
7-1 RESERVED R/W 0h
0 ENABLE R/W 0h This bit enables the DAC module.
0h = DAC is disabled
1h = DAC is enabled

14.3.21 CTL1 (Offset = 1110h) [Reset = 00000000h]

CTL1 is shown in Figure 14-28 and described in Table 14-29.

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Control 1 register.

Figure 14-28 CTL1
31 30 29 28 27 26 25 24
RESERVED OPS
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED REFSN REFSP
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED AMPHIZ AMPEN
R/W-0h R/W-0h R/W-0h
Table 14-29 CTL1 Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R/W 0h
24 OPS R/W 0h These bits select the DAC output on device pin.
0h = No connect. Both DAC output switches are open.
1h = OUT0 output is selected
23-10 RESERVED R/W 0h
9 REFSN R/W 0h This bit selects the DAC voltage reference source + input.
0h = VEREFN pin as VR-
1h = Analog supply (VSSA) as VR-
8 REFSP R/W 0h This bit selects the DAC voltage reference source + input.
0h = Analog supply (VDDA) as VR+
1h = VEREFP pin as VR+
7-2 RESERVED R/W 0h
1 AMPHIZ R/W 0h AMPHIZ - amplifier output value

0 : amplifier output is high impedance
1 : amplifier output is pulled down to ground
0h = HiZ when disable
1h = dacout pulldown when disable
0 AMPEN R/W 0h AMP_EN - output amplifier enabled or disabled
0 : disabled
1 : enabled
0h = disable
1h = enable

14.3.22 CTL2 (Offset = 1120h) [Reset = 00000000h]

CTL2 is shown in Figure 14-29 and described in Table 14-30.

Return to the Summary Table.

Control 2 register.

Figure 14-29 CTL2
31 30 29 28 27 26 25 24
RESERVED DMATRIGEN
R/W-0h RH/W-0h
23 22 21 20 19 18 17 16
RESERVED FIFOTRIGSEL
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FIFOTH
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFOEN
R/W-0h R/W-0h
Table 14-30 CTL2 Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R/W 0h
24 DMATRIGEN RH/W 0h This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN, the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit should be cleared by software to stop further DMA triggers.
0h = DMA trigger generation mechanism is disabled
1h = DMA trigger generation mechanism is enabled
23-18 RESERVED R/W 0h
17-16 FIFOTRIGSEL R/W 0h These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted, the data from FIFO (as indicated by read pointer) is moved into internal DAC data register.
0h = Sample time generator output
1h = Hardware trigger-0 from event fabric
2h = Reserved - unimplemented
3h = Reserved - unimplemented
15-10 RESERVED R/W 0h
9-8 FIFOTH R/W 0h These bits determine the FIFO threshold. In case of DMA based operation, DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level. In case of CPU based operation, the FIFO threshold bits are don't care and FIFO level is directly indicated through the respective bits in the RIS register.
0h = One fourth of the FIFO locations are empty
1h = Half of the FIFO locations are empty
2h = Three fourth of the FIFO locations are empty
3h = Reserved value. Defaults to same effect as FIFOTH = 0 (One fourth of the FIFO locations are empty).
7-1 RESERVED R/W 0h
0 FIFOEN R/W 0h This bit enables the FIFO and the FIFO hardware control state machine.
0h = FIFO is disabled
1h = FIFO is enabled

14.3.23 CTL3 (Offset = 1130h) [Reset = 00000000h]

CTL3 is shown in Figure 14-30 and described in Table 14-31.

Return to the Summary Table.

Control 3 register.

Figure 14-30 CTL3
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED STIMCONFIG
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED STIMEN
R/W-0h R/W-0h
Table 14-31 CTL3 Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R/W 0h
11-8 STIMCONFIG R/W 0h These bits are used to configure the trigger rate from the sample time generator. The STIMCONFIG values 10 to 15 are reserved and default to same effect as value 0 (500SPS).
0h = Trigger rate is 500 sps (clock divide value is 4000)
1h = Trigger rate is 1 ksps (clock divide value is 2000)
2h = Trigger rate is 2 ksps (clock divide value is 1000)
3h = Trigger rate is 4 ksps (clock divide value is 500)
4h = Trigger rate is 8 ksps (clock divide value is 250)
5h = Trigger rate is 16 ksps (clock divide value is 125)
6h = Trigger rate is 100 ksps (clock divide value is 20)
7h = Trigger rate is 200 ksps (clock divide value is 10)
8h = Trigger rate is 500 ksps (clock divide value is 4)
9h = Trigger rate is 1 Msps (clock divide value is 2)
7-1 RESERVED R/W 0h
0 STIMEN R/W 0h This bit enables the sample time generator.
0h = Sample time generator is disabled
1h = Sample time generator is enabled

14.3.24 CALCTL (Offset = 1140h) [Reset = 00000000h]

CALCTL is shown in Figure 14-31 and described in Table 14-32.

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Calibration control register.

Figure 14-31 CALCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED CALSEL CALON
R/W-0h RH/W-0h RH/W-0h
Table 14-32 CALCTL Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R/W 0h
1 CALSEL RH/W 0h This bit is used to select between factory trim or self calibration trim.
0h (R/W) = Factory Trim : Factory Trim Calibration Values are used when calibration is enabled
1h (R/W) = Self Calibration Trim : Self Calibration Trim Values are used when calibration is enabled
0 CALON RH/W 0h This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes.
0h = Offset error calibration is not active
1h = Initiate offset error calibration or offset error calibration is already in progress

14.3.25 CALDATA (Offset = 1160h) [Reset = 00000000h]

CALDATA is shown in Figure 14-32 and described in Table 14-33.

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This is the offset error calibration data register.

Figure 14-32 CALDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R-0h RH-0h
Table 14-33 CALDATA Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h
6-0 DATA RH 0h DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of –64 to +63.
This is read-only bit, reflecting the calibration data. Writing to this register will have no effect, it will not change the calibration value.

14.3.26 DATA0 (Offset = 1200h) [Reset = 00000000h]

DATA0 is shown in Figure 14-33 and described in Table 14-34.

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Data 0 register. This register can be written with one 8-bit or one 12-bit digital input data.

Figure 14-33 DATA0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA_VALUE
R/W-0h R/W-0h
Table 14-34 DATA0 Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R/W 0h
11-0 DATA_VALUE R/W 0h This is the data written for digital to analog conversion.