SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

16.3 UART Registers

Table 16-12 lists the memory-mapped registers for the UART registers. All register offset addresses not listed in Table 16-12 should be considered as reserved locations and the register contents should not be modified.

Table 16-12 UART Registers
Offset Acronym Register Name Group Section
800h PWREN Power enable Go
804h RSTCTL Reset Control Go
808h CLKCFG Peripheral Clock Configuration Register Go
814h STAT Status Register Go
1000h CLKDIV Clock Divider Go
1008h CLKSEL Clock Select for Ultra Low Power peripherals Go
1018h PDBGCTL Peripheral Debug Control Go
1020h IIDX Interrupt index CPU_INT Go
1028h IMASK Interrupt mask CPU_INT Go
1030h RIS Raw interrupt status CPU_INT Go
1038h MIS Masked interrupt status CPU_INT Go
1040h ISET Interrupt set CPU_INT Go
1048h ICLR Interrupt clear CPU_INT Go
1050h IIDX Interrupt index DMA_TRIG_RX Go
1058h IMASK Interrupt mask DMA_TRIG_RX Go
1060h RIS Raw interrupt status DMA_TRIG_RX Go
1068h MIS Masked interrupt status DMA_TRIG_RX Go
1070h ISET Interrupt set DMA_TRIG_RX Go
1078h ICLR Interrupt clear DMA_TRIG_RX Go
1080h IIDX Interrupt index DMA_TRIG_TX Go
1088h IMASK Interrupt mask DMA_TRIG_TX Go
1090h RIS Raw interrupt status DMA_TRIG_TX Go
1098h MIS Masked interrupt status DMA_TRIG_TX Go
10A0h ISET Interrupt set DMA_TRIG_TX Go
10A8h ICLR Interrupt clear DMA_TRIG_TX Go
10E0h EVT_MODE Event Mode Go
10E4h INTCTL Interrupt control register Go
1100h CTL0 UART Control Register 0 Go
1104h LCRH UART Line Control Register Go
1108h STAT UART Status Register Go
110Ch IFLS UART Interrupt FIFO Level Select Register Go
1110h IBRD UART Integer Baud-Rate Divisor Register Go
1114h FBRD UART Fractional Baud-Rate Divisor Register Go
1118h GFCTL Glitch Filter Control Go
1120h TXDATA UART Transmit Data Register Go
1124h RXDATA UART Receive Data Register Go
1130h LINCNT UART LIN Mode Counter Register Go
1134h LINCTL UART LIN Mode Control Register Go
1138h LINC0 UART LIN Mode Capture 0 Register Go
113Ch LINC1 UART LIN Mode Capture 1 Register Go
1140h IRCTL eUSCI_Ax IrDA Control Word Register Go
1148h AMASK Self Address Mask Register Go
114Ch ADDR Self Address Register Go
1160h CLKDIV2 Clock Divider Go

Complex bit access types are encoded to fit into small table cells. Table 16-13 shows the codes that are used for access types in this section.

Table 16-13 UART Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
WK W
K		 Write
Write protected by a key
Reset or Default Value
-n Value after reset or the default value

16.3.1 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 16-16 and described in Table 16-14.

Return to the Summary Table.

Register to control the power state

Figure 16-16 PWREN
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE
R/W-0h R/WK-0h
Table 16-14 PWREN Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to allow Power State Change
26h = KEY to allow write access to this register
23-1 RESERVED R/W 0h
0 ENABLE R/WK 0h Enable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

16.3.2 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 16-17 and described in Table 16-15.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 16-17 RSTCTL
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED RESETSTKYCLR RESETASSERT
W-0h WK-0h WK-0h
Table 16-15 RSTCTL Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h Unlock key
B1h = KEY to allow write access to this register
23-2 RESERVED W 0h
1 RESETSTKYCLR WK 0h Clear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0 RESETASSERT WK 0h Assert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

16.3.3 CLKCFG (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 16-18 and described in Table 16-16.

Return to the Summary Table.

Peripheral Clock Configuration Register

Figure 16-18 CLKCFG
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED BLOCKASYNC
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Table 16-16 CLKCFG Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to Allow State Change -- 0xA9
A9h = 0xA9
23-9 RESERVED R/W 0h
8 BLOCKASYNC R/W 0h Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0h = 0
1h = 1
7-0 RESERVED R/W 0h

16.3.4 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 16-19 and described in Table 16-17.

Return to the Summary Table.

Reset status register

Figure 16-19 STAT
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED RESETSTKY
R- R-0h
15 14 13 12 11 10 9 8
RESERVED
R-
7 6 5 4 3 2 1 0
RESERVED
R-
Table 16-17 STAT Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 RESETSTKY R 0h This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0 RESERVED R 0h

16.3.5 CLKDIV (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 16-20 and described in Table 16-18.

Return to the Summary Table.

This register is used to specify module-specific divide ratio of the functional clock

Figure 16-20 CLKDIV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RATIO
R/W-0h R/W-0h
Table 16-18 CLKDIV Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R/W 0h
2-0 RATIO R/W 0h Selects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

16.3.6 CLKSEL (Offset = 1008h) [Reset = 00000000h]

CLKSEL is shown in Figure 16-21 and described in Table 16-19.

Return to the Summary Table.

Clock source selection for peripherals

Figure 16-21 CLKSEL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED BUSCLK_SEL MFCLK_SEL LFCLK_SEL RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 16-19 CLKSEL Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3 BUSCLK_SEL R/W 0h Selects BUS CLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
2 MFCLK_SEL R/W 0h Selects MFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
1 LFCLK_SEL R/W 0h Selects LFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
0 RESERVED R/W 0h

16.3.7 PDBGCTL (Offset = 1018h) [Reset = 00000003h]

PDBGCTL is shown in Figure 16-22 and described in Table 16-20.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 16-22 PDBGCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED SOFT FREE
R/W- R/W-1h R/W-1h
Table 16-20 PDBGCTL Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R/W 0h
1 SOFT R/W 1h Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0 FREE R/W 1h Free run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

16.3.8 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 16-23 and described in Table 16-21.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 16-23 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 16-21 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved
00h = No interrupt pending
01h = UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest
02h = UART framing error interrupt; Interrupt Flag: FE
03h = UART parity error interrupt; Interrupt Flag: PE
04h = UART break error interrupt; Interrupt Flag: BE
05h = UART receive overrun error interrupt; Interrupt Flag: OE
06h = Negative edge on UARTxRXD interrupt; Interrupt Flag: RXNE
07h = Positive edge on UARTxRXD interrupt; Interrupt Flag: RXPE
08h = LIN capture 0 / match interrupt; Interrupt Flag: LINC0
09h = LIN capture 1 interrupt; Interrupt Flag: LINC1
0Ah = LIN hardware counter overflow interrupt; Interrupt Flag: LINOVF
0Bh = UART receive interrupt; Interrupt Flag: RX
0Ch = UART transmit interrupt; Interrupt Flag: TX
0Dh = UART end of transmission interrupt (transmit serializer empty); Interrupt Flag: EOT
0Eh = 9-bit mode address match interrupt; Interrupt Flag: MODE_9B
Fh = UART Clear to Send Modem interrupt; Interrupt Flag: CTS
10h = DMA DONE on RX
11h = DMA DONE on TX
12h = Noise Error Event

16.3.9 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 16-24 and described in Table 16-22.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 16-24 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED NERR DMA_DONE_TX
R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
DMA_DONE_RX CTS ADDR_MATCH EOT TXINT RXINT LINOVF LINC1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LINC0 RXPE RXNE OVRERR BRKERR PARERR FRMERR RTOUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 16-22 IMASK Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R/W 0h
17 NERR R/W 0h Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
16 DMA_DONE_TX R/W 0h Enable DMA Done on TX Event Channel Interrupt
0h = Interrupt disabled
1h = Set Interrupt Mask
15 DMA_DONE_RX R/W 0h Enable DMA Done on RX Event Channel Interrupt
0h = Interrupt disabled
1h = Set Interrupt Mask
14 CTS R/W 0h Enable UART Clear to Send Modem Interrupt.
0h = Interrupt disabled
1h = Set Interrupt Mask
13 ADDR_MATCH R/W 0h Enable Address Match Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12 EOT R/W 0h Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11 TXINT R/W 0h Enable UART Transmit Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10 RXINT R/W 0h Enable UART Receive Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9 LINOVF R/W 0h Enable LIN Hardware Counter Overflow Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8 LINC1 R/W 0h Enable LIN Capture 1 Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7 LINC0 R/W 0h Enable LIN Capture 0 / Match Interrupt .
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6 RXPE R/W 0h Enable Positive Edge on UARTxRXD Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5 RXNE R/W 0h Enable Negative Edge on UARTxRXD Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4 OVRERR R/W 0h Enable UART Receive Overrun Error Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3 BRKERR R/W 0h Enable UART Break Error Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2 PARERR R/W 0h Enable UART Parity Error Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1 FRMERR R/W 0h Enable UART Framing Error Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0 RTOUT R/W 0h Enable UARTOUT Receive Time-Out Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

16.3.10 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 16-25 and described in Table 16-23.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 16-25 RIS
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED NERR DMA_DONE_TX
R- R-0h R-0h
15 14 13 12 11 10 9 8
DMA_DONE_RX CTS ADDR_MATCH EOT TXINT RXINT LINOVF LINC1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
LINC0 RXPE RXNE OVRERR BRKERR PARERR FRMERR RTOUT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 16-23 RIS Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 NERR R 0h Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0h = Interrupt did not occur
1h = Interrupt occurred
16 DMA_DONE_TX R 0h DMA Done on TX Event Channel Interrupt
0h = Interrupt disabled
1h = Interrupt occurred
15 DMA_DONE_RX R 0h DMA Done on RX Event Channel Interrupt
0h = Interrupt disabled
1h = Interrupt occurred
14 CTS R 0h UART Clear to Send Modem Interrupt.
0h = Interrupt disabled
1h = Interrupt occurred
13 ADDR_MATCH R 0h Address Match Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
12 EOT R 0h UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer.
0h = Interrupt did not occur
1h = Interrupt occurred
11 TXINT R 0h UART Transmit Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
10 RXINT R 0h UART Receive Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
9 LINOVF R 0h LIN Hardware Counter Overflow Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
8 LINC1 R 0h LIN Capture 1 Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
7 LINC0 R 0h LIN Capture 0 / Match Interrupt .
0h = Interrupt did not occur
1h = Interrupt occurred
6 RXPE R 0h Positive Edge on UARTxRXD Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
5 RXNE R 0h Negative Edge on UARTxRXD Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
4 OVRERR R 0h UART Receive Overrun Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
3 BRKERR R 0h UART Break Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
2 PARERR R 0h UART Parity Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
1 FRMERR R 0h UART Framing Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
0 RTOUT R 0h UARTOUT Receive Time-Out Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred

16.3.11 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 16-26 and described in Table 16-24.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 16-26 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED NERR DMA_DONE_TX
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
DMA_DONE_RX CTS ADDR_MATCH EOT TXINT RXINT LINOVF LINC1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
LINC0 RXPE RXNE OVRERR BRKERR PARERR FRMERR RTOUT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 16-24 MIS Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 NERR R 0h Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0h = Interrupt did not occur
1h = Interrupt occurred
16 DMA_DONE_TX R 0h Masked DMA Done on TX Event Channel Interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
15 DMA_DONE_RX R 0h Masked DMA Done on RX Event Channel Interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
14 CTS R 0h Masked UART Clear to Send Modem Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
13 ADDR_MATCH R 0h Masked Address Match Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
12 EOT R 0h UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer.
0h = Interrupt did not occur
1h = Interrupt occurred
11 TXINT R 0h Masked UART Transmit Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
10 RXINT R 0h Masked UART Receive Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
9 LINOVF R 0h Masked LIN Hardware Counter Overflow Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
8 LINC1 R 0h Masked LIN Capture 1 Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
7 LINC0 R 0h Masked LIN Capture 0 / Match Interrupt .
0h = Interrupt did not occur
1h = Interrupt occurred
6 RXPE R 0h Masked Positive Edge on UARTxRXD Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
5 RXNE R 0h Masked Negative Edge on UARTxRXD Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
4 OVRERR R 0h Masked UART Receive Overrun Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
3 BRKERR R 0h Masked UART Break Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
2 PARERR R 0h Masked UART Parity Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
1 FRMERR R 0h Masked UART Framing Error Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
0 RTOUT R 0h Masked UARTOUT Receive Time-Out Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred

16.3.12 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 16-27 and described in Table 16-25.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 16-27 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED NERR DMA_DONE_TX
W-0h W-0h W-0h
15 14 13 12 11 10 9 8
DMA_DONE_RX CTS ADDR_MATCH EOT TXINT RXINT LINOVF LINC1
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
LINC0 RXPE RXNE OVRERR BRKERR PARERR FRMERR RTOUT
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 16-25 ISET Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED W 0h
17 NERR W 0h Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0h = Writing this has no effect
1h = Set the interrupt
16 DMA_DONE_TX W 0h Set DMA Done on TX Event Channel Interrupt
0h = Interrupt disabled
1h = Set Interrupt
15 DMA_DONE_RX W 0h Set DMA Done on RX Event Channel Interrupt
0h = Interrupt disabled
1h = Set Interrupt
14 CTS W 0h Set UART Clear to Send Modem Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
13 ADDR_MATCH W 0h Set Address Match Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
12 EOT W 0h Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer.
0h = Writing 0 has no effect
1h = Set Interrupt
11 TXINT W 0h Set UART Transmit Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
10 RXINT W 0h Set UART Receive Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
9 LINOVF W 0h Set LIN Hardware Counter Overflow Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
8 LINC1 W 0h Set LIN Capture 1 Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
7 LINC0 W 0h Set LIN Capture 0 / Match Interrupt .
0h = Writing 0 has no effect
1h = Set Interrupt
6 RXPE W 0h Set Positive Edge on UARTxRXD Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
5 RXNE W 0h Set Negative Edge on UARTxRXD Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
4 OVRERR W 0h Set UART Receive Overrun Error Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
3 BRKERR W 0h Set UART Break Error Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
2 PARERR W 0h Set UART Parity Error Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
1 FRMERR W 0h Set UART Framing Error Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
0 RTOUT W 0h Set UARTOUT Receive Time-Out Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt

16.3.13 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 16-28 and described in Table 16-26.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 16-28 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED NERR DMA_DONE_TX
W-0h W-0h W-0h
15 14 13 12 11 10 9 8
DMA_DONE_RX CTS ADDR_MATCH EOT TXINT RXINT LINOVF LINC1
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
LINC0 RXPE RXNE OVRERR BRKERR PARERR FRMERR RTOUT
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 16-26 ICLR Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED W 0h
17 NERR W 0h Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal
0h = Writing 0 has no effect
1h = Clear Interrupt
16 DMA_DONE_TX W 0h Clear DMA Done on TX Event Channel Interrupt
0h = Interrupt disabled
1h = Clear Interrupt
15 DMA_DONE_RX W 0h Clear DMA Done on RX Event Channel Interrupt
0h = Interrupt disabled
1h = Clear Interrupt
14 CTS W 0h Clear UART Clear to Send Modem Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
13 ADDR_MATCH W 0h Clear Address Match Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
12 EOT W 0h Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX FIFO or Buffer.
0h = Writing 0 has no effect
1h = Clear Interrupt
11 TXINT W 0h Clear UART Transmit Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
10 RXINT W 0h Clear UART Receive Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
9 LINOVF W 0h Clear LIN Hardware Counter Overflow Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
8 LINC1 W 0h Clear LIN Capture 1 Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
7 LINC0 W 0h Clear LIN Capture 0 / Match Interrupt .
0h = Writing 0 has no effect
1h = Clear Interrupt
6 RXPE W 0h Clear Positive Edge on UARTxRXD Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
5 RXNE W 0h Clear Negative Edge on UARTxRXD Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
4 OVRERR W 0h Clear UART Receive Overrun Error Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
3 BRKERR W 0h Clear UART Break Error Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
2 PARERR W 0h Clear UART Parity Error Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
1 FRMERR W 0h Clear UART Framing Error Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
0 RTOUT W 0h Clear UARTOUT Receive Time-Out Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt

16.3.14 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 16-29 and described in Table 16-27.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 16-29 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 16-27 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
00h = No interrupt pending
01h = UART receive time-out interrupt; Interrupt Flag: RT; Interrupt Priority: Highest
0Bh = UART receive interrupt; Interrupt Flag: RX

16.3.15 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 16-30 and described in Table 16-28.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 16-30 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED RXINT RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED RTOUT
R/W-0h R/W-0h
Table 16-28 IMASK Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R/W 0h
10 RXINT R/W 0h Enable UART Receive Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9-1 RESERVED R/W 0h
0 RTOUT R/W 0h Enable UARTOUT Receive Time-Out Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

16.3.16 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 16-31 and described in Table 16-29.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 16-31 RIS
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
RESERVED RXINT RESERVED
R- R-0h R-
7 6 5 4 3 2 1 0
RESERVED RTOUT
R- R-0h
Table 16-29 RIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXINT R 0h UART Receive Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
9-1 RESERVED R 0h
0 RTOUT R 0h UARTOUT Receive Time-Out Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred

16.3.17 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 16-32 and described in Table 16-30.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 16-32 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXINT RESERVED
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RTOUT
R-0h R-0h
Table 16-30 MIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXINT R 0h Masked UART Receive Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
9-1 RESERVED R 0h
0 RTOUT R 0h Masked UARTOUT Receive Time-Out Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred

16.3.18 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 16-33 and described in Table 16-31.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 16-33 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED RXINT RESERVED
W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED RTOUT
W-0h W-0h
Table 16-31 ISET Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED W 0h
10 RXINT W 0h Set UART Receive Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
9-1 RESERVED W 0h
0 RTOUT W 0h Set UARTOUT Receive Time-Out Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt

16.3.19 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 16-34 and described in Table 16-32.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 16-34 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED RXINT RESERVED
W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED RTOUT
W-0h W-0h
Table 16-32 ICLR Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED W 0h
10 RXINT W 0h Clear UART Receive Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
9-1 RESERVED W 0h
0 RTOUT W 0h Clear UARTOUT Receive Time-Out Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt

16.3.20 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 16-35 and described in Table 16-33.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 16-35 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 16-33 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h UART Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved
00h = No interrupt pending
0Ch = UART transmit interrupt; Interrupt Flag: TX

16.3.21 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 16-36 and described in Table 16-34.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 16-36 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED TXINT RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Table 16-34 IMASK Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R/W 0h
11 TXINT R/W 0h Enable UART Transmit Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10-0 RESERVED R/W 0h

16.3.22 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 16-37 and described in Table 16-35.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 16-37 RIS
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
RESERVED TXINT RESERVED
R- R-0h R-
7 6 5 4 3 2 1 0
RESERVED
R-
Table 16-35 RIS Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 TXINT R 0h UART Transmit Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
10-0 RESERVED R 0h

16.3.23 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 16-38 and described in Table 16-36.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 16-38 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED TXINT RESERVED
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 16-36 MIS Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 TXINT R 0h Masked UART Transmit Interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
10-0 RESERVED R 0h

16.3.24 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 16-39 and described in Table 16-37.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 16-39 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED TXINT RESERVED
W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED
W-0h
Table 16-37 ISET Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED W 0h
11 TXINT W 0h Set UART Transmit Interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
10-0 RESERVED W 0h

16.3.25 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 16-40 and described in Table 16-38.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 16-40 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED TXINT RESERVED
W-0h W-0h W-0h
7 6 5 4 3 2 1 0
RESERVED
W-0h
Table 16-38 ICLR Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED W 0h
11 TXINT W 0h Clear UART Transmit Interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
10-0 RESERVED W 0h

16.3.26 EVT_MODE (Offset = 10E0h) [Reset = 00000029h]

EVT_MODE is shown in Figure 16-41 and described in Table 16-39.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 16-41 EVT_MODE
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED INT2_CFG INT1_CFG INT0_CFG
R/W- R-2h R-2h R-1h
Table 16-39 EVT_MODE Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R/W 0h
5-4 INT2_CFG R 2h Event line mode select for event corresponding to none.DMA_TRIG_TX
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2 INT1_CFG R 2h Event line mode select for event corresponding to none.DMA_TRIG_RX
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0 INT0_CFG R 1h Event line mode select for event corresponding to none.CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

16.3.27 INTCTL (Offset = 10E4h) [Reset = 00000000h]

INTCTL is shown in Figure 16-42 and described in Table 16-40.

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Interrupt control register

Figure 16-42 INTCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED INTEVAL
R/W- W-0h
Table 16-40 INTCTL Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R/W 0h
0 INTEVAL W 0h Writing a 1 to this field re-evaluates the interrupt sources.
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.

16.3.28 CTL0 (Offset = 1100h) [Reset = 00000038h]

CTL0 is shown in Figure 16-43 and described in Table 16-41.

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UART Control Register
The CTL0 register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set. To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. NOTE: The CTL0 register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the CTL0 register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit FEN in the UART control register CTL0.
4. Reprogram the control register.
5. Enable the UART.

Figure 16-43 CTL0
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED MSBFIRST MAJVOTE FEN HSE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
HSE CTSEN RTSEN RTS RESERVED MODE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
MENC TXD_OUT TXD_OUT_EN TXE RXE LBE RESERVED ENABLE
R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h
Table 16-41 CTL0 Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R/W 0h
19 MSBFIRST R/W 0h Most Significant Bit First
This bit has effect both on the way protocol byte is transmitted and received.
Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.
0h = Least significant bit is sent first in the protocol packet
1h = Most significant bit is sent first in the protocol packet
18 MAJVOTE R/W 0h Majority Vote Enable

When Majority Voting is enabled, the three center bits are used to determine received sample value. In case of error (i.e. all 3 bits are not the same), noise error is detected and bits RIS.NERR and register RXDATA.NERR are set.
Oversampling of 16 : bits 7, 8, 9 are used
Oversampling of 8 : bits 3, 4, 5 are used
Disabled : Single sample value (center value) used
0h = Majority voting is disabled
1h = Majority voting is enabled
17 FEN R/W 0h UART Enable FIFOs
0h = The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
1h = The transmit and receive FIFO buffers are enabled (FIFO mode).
16-15 HSE R/W 0h High-Speed Bit Oversampling Enable NOTE: The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).
0h = 16x oversampling.
1h = 8x oversampling.
2h = 3x oversampling. IrDA, Manchester and DALI not supported when 3x oversampling is enabled.
14 CTSEN R/W 0h Enable Clear To Send
0h = CTS hardware flow control is disabled.
1h = CTS hardware flow control is enabled. Data is only transmitted when the UARTxCTS signal is asserted.
13 RTSEN R/W 0h Enable hardware controlled Request to Send
0h = RTS hardware flow control is disabled.
1h = RTS hardware flow control is enabled. Data is only requested (by asserting UARTxRTS) when the receive FIFO has available entries.
12 RTS R/W 0h Request to Send
If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer.
If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.
0h = Signal not RTS
1h = Signal RTS
11 RESERVED R/W 0h
10-8 MODE R/W 0h Set the communication mode and protocol used.
(Not defined settings uses the default setting: 0)
0h = Normal operation
1h = RS485 mode: UART needs to be IDLE with receiving data for the in EXTDIR_HOLD set time. EXTDIR_SETUP defines the time the RTS line is set to high before sending. When the buffer is empty the RTS line is set low again. A transmit will be delayed as long the UART is receiving data.
2h = The UART operates in IDLE Line Mode
3h = The UART operates in 9 Bit Address mode
4h = ISO7816 Smart Card Support The application must ensure that it sets 8-bit word length (WLEN set to 3h) and even parity (PEN set to 1, EPS set to 1, SPS set to 0) in UARTLCRH when using ISO7816 mode. The value of the STP2 bit in UARTLCRH is ignored and the number of stop bits is forced to 2.
5h = DALI Mode:
7 MENC R/W 0h Manchester Encode enable
0h = Disable Manchester Encoding
1h = Enable Manchester Encoding
6 TXD_OUT R/W 0h TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.

0h = TXD pin is low
1h = TXD pin is high
5 TXD_OUT_EN R/W 1h TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit.
0h = TXD pin can not be controlled by TXD_OUT
1h = TXD pin can be controlled by TXD_OUT
4 TXE R/W 1h UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. NOTE: To enable transmission, the UARTEN bit must be set.
0h = The transmit section of the UART is disabled. The UARTxTXD pin of the UART can be controlled by the TXD_CTL bit when enabled.
1h = The transmit section of the UART is enabled.
3 RXE R/W 1h UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. NOTE: To enable reception, the UARTEN bit must be set.
0h = The receive section of the UART is disabled.
1h = The receive section of the UART is enabled.
2 LBE R/W 0h UART Loop Back Enable
0h = Normal operation.
1h = The UARTxTX path is fed through the UARTxRX path internally.
1 RESERVED R/W 0h
0 ENABLE R/W 0h UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.
If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update.
If disabled the UART module will not send or receive any data and the logic is held in reset state.
0h = Disable Module
1h = Enable module

16.3.29 LCRH (Offset = 1104h) [Reset = 00000000h]

LCRH is shown in Figure 16-44 and described in Table 16-42.

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UART Line Control Register The LCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD or UARTIFRD), the LCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the LCRH register.

Figure 16-44 LCRH
31 30 29 28 27 26 25 24
RESERVED EXTDIR_HOLD
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
EXTDIR_HOLD EXTDIR_SETUP
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
SENDIDLE SPS WLEN STP2 EPS PEN BRK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 16-42 LCRH Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R/W 0h
25-21 EXTDIR_HOLD R/W 0h Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)
0h = Smallest value
1Fh = Highest possible value
20-16 EXTDIR_SETUP R/W 0h Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send
0h = Smallest value
1Fh = Highest possible value
15-8 RESERVED R/W 0h
7 SENDIDLE R/W 0h UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterward.
0h = Disable Send Idle Pattern
1h = Enable Send Idle Pattern
6 SPS R/W 0h UART Stick Parity Select
The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network.

When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0.
When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1.

0h = Disable Stick Parity
1h = Enable Stick Parity
5-4 WLEN R/W 0h UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:
0h = 5 bits (default)
1h = 6 bits
2h = 7 bits
3h = 8 bits
3 STP2 R/W 0h UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.
0h = One stop bit is transmitted at the end of a frame.
1h = Two stop bits are transmitted at the end of a frame. The receive logic checks for two stop bits being received and provide Frame Error if either is invalid.
2 EPS R/W 0h UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte
0h = Odd parity is performed, which checks for an odd number of 1s.
1h = Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits.
1 PEN R/W 0h UART Parity Enable
0h = Parity is disabled and no parity bit is added to the data frame.
1h = Parity checking and generation is enabled.
0 BRK R/W 0h UART Send Break (for LIN Protocol)
0h = Normal use.
1h = A low level is continually output on the UARTxTXD signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods).

16.3.30 STAT (Offset = 1108h) [Reset = 00000144h]

STAT is shown in Figure 16-45 and described in Table 16-43.

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UART Status Register

Figure 16-45 STAT
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
RESERVED IDLE CTS
R- R-0h R-1h
7 6 5 4 3 2 1 0
TXFF TXFE RESERVED RXFF RXFE RESERVED BUSY
R-0h R-1h R- R-0h R-1h R- R-0h
Table 16-43 STAT Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h
9 IDLE R 0h IDLE mode has been detected in Idleline-Multiprocessor-Mode.
The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address.
0h = IDLE has not been detected before last received character.
(In idle-line multiprocessor mode).
1h = IDLE has been detected before last received character.
(In idle-line multiprocessor mode).
8 CTS R 1h Clear To Send
0h = The CTS signal is not asserted (high).
1h = The CTS signal is asserted (low).
7 TXFF R 0h UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0h = The transmitter is not full.
1h = If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
6 TXFE R 1h UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0h = The transmitter has data to transmit.
1h = If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
5-4 RESERVED R 0h
3 RXFF R 0h UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0h = The receiver can receive data.
1h = If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the receive FIFO is full.
2 RXFE R 1h UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.
0h = The receiver is not empty.
1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty. If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
1 RESERVED R 0h
0 BUSY R 0h UART Busy
This bit is set as soon as the transmit FIFO or TXDATA register becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register).
In IDLE_Line mode the Busy signal also stays set during the idle time generation.
0h = The UART is not busy.
1h = The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent/received from/into the shift register.

16.3.31 IFLS (Offset = 110Ch) [Reset = 00000022h]

IFLS is shown in Figure 16-46 and described in Table 16-44.

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The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 16-46 IFLS
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED RXTOSEL
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED RXIFLSEL RESERVED TXIFLSEL
R/W-0h R/W-2h R/W-0h R/W-2h
Table 16-44 IFLS Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R/W 0h
11-8 RXTOSEL R/W 0h UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bit times a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function.
0h = Smallest value
Fh = Highest possible value
7 RESERVED R/W 0h
6-4 RXIFLSEL R/W 2h UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:

Note:
In ULP domain the trigger levels are used for:
0: LVL_1_4
4: LVL_FULL
For undefined settings the default configuration is used.
0h = RX FIFO >= 1/4 full
Note: For ULP Domain
1h = RX FIFO >= 1/4 full
2h = RX FIFO >= 1/2 full (default)
3h = RX FIFO >= 3/4 full
4h = RX FIFO is full
Note: For ULP Domain
5h = RX FIFO is full
7h = RX FIFO >= 1 entry available
Note: esp. required for DMA Trigger
3 RESERVED R/W 0h
2-0 TXIFLSEL R/W 2h UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
Note: for undefined settings the default configuration is used.
1h = TX FIFO <= 3/4 empty
2h = TX FIFO <= 1/2 empty (default)
3h = TX FIFO <= 1/4 empty
5h = TX FIFO is empty
7h = TX FIFO >= 1 entry free
Note: esp. required for DMA Trigger

16.3.32 IBRD (Offset = 1110h) [Reset = 00000000h]

IBRD is shown in Figure 16-47 and described in Table 16-45.

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When changing the IBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See Baud-Rate Generation chapter for configuration details.

Figure 16-47 IBRD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DIVINT
R/W-0h R/W-0h
Table 16-45 IBRD Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R/W 0h
15-0 DIVINT R/W 0h Integer Baud-Rate Divisor
0h = Smallest value
FFFFh = Highest possible value

16.3.33 FBRD (Offset = 1114h) [Reset = 00000000h]

FBRD is shown in Figure 16-48 and described in Table 16-46.

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UART Fractional Baud-Rate Divisor Register The FBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the FBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See Baud-Rate Generation chapter for configuration details.

Figure 16-48 FBRD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DIVFRAC
R/W-0h R/W-0h
Table 16-46 FBRD Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R/W 0h
5-0 DIVFRAC R/W 0h Fractional Baud-Rate Divisor
0h = Smallest value
3Fh = Highest possible value

16.3.34 GFCTL (Offset = 1118h) [Reset = X]

GFCTL is shown in Figure 16-49 and described in Table 16-47.

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This register control the glitch filter on the RX input.

Figure 16-49 GFCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED CHAIN AGFSEL AGFEN
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DGFSEL
R/W-0h R/W-0h
Table 16-47 GFCTL Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R/W 0h
11 CHAIN R/W 0h Analog and digital noise filters chaining enable.
0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling
1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling

0h = Disabled
1h = Enabled
10-9 AGFSEL R/W 0h Analog Glitch Suppression Pulse Width

This field controls the pulse width select for the analog glitch suppression on the RX line.
See device data sheet for exact values.
0h = Pulses shorter then 5ns length are filtered.
1h = Pulses shorter then 10ns length are filtered.
2h = Pulses shorter then 25ns length are filtered.
3h = Pulses shorter then 50ns length are filtered.
8 AGFEN R/W 0h Analog Glitch Suppression Enable
0h = Analog Glitch Filter disable
1h = Analog Glitch Filter enable
7-6 RESERVED R/W 0h
5-0 DGFSEL R/W 0h Glitch Suppression Pulse Width

This field controls the pulse width select for glitch suppression on the RX line.
The value programmed in this field gives the number of cycles of functional clock up to which the glitch has to be suppressed on the RX line.

In IRDA mode:
The minimum pulse length for receive is given by:
t(MIN) = (DGFSEL) / f(IRTXCLK)

0h = Bypass GF
3Fh = Highest Possible Value

16.3.35 TXDATA (Offset = 1120h) [Reset = 00000000h]

TXDATA is shown in Figure 16-50 and described in Table 16-48.

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UART Transmit Data Register. This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART.

Figure 16-50 TXDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R/W-0h R/W-0h
Table 16-48 TXDATA Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R/W 0h
7-0 DATA R/W 0h Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART.
0h = Smallest value
FFh = Highest possible value

16.3.36 RXDATA (Offset = 1124h) [Reset = 00000000h]

RXDATA is shown in Figure 16-51 and described in Table 16-49.

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UART Receive Data Register. This register is the data receive register (the interface to the FIFOs). For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Figure 16-51 RXDATA
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED NERR OVRERR BRKERR PARERR FRMERR
R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DATA
R-0h
Table 16-49 RXDATA Field Descriptions
Bit Field Type Reset Description
31-13 RESERVED R 0h
12 NERR R 0h Noise Error.
Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register.
0h = No noise error occurred
1h = Noise error occurred during majority voting
11 OVRERR R 0h UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.
0h = No data has been lost due to a receive overrun.
1h = New data was received but could not be stored, because the previous data was not read (resulting in data loss).
10 BRKERR R 0h UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
0h = No break condition has occurred
1h = A break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
9 PARERR R 0h UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register.
0h = No parity error has occurred
1h = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.
8 FRMERR R 0h UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO.
0h = No framing error has occurred
1h = The received character does not have a valid stop bit sequence, which is one or two stop bits depending on the UARTLCRH.STP2 setting (a valid stop bit is 1).
7-0 DATA R 0h Received Data. When read, this field contains the data that was received by the UART.
0h = Smallest value
FFh = Highest possible value

16.3.37 LINCNT (Offset = 1130h) [Reset = 00000000h]

LINCNT is shown in Figure 16-52 and described in Table 16-50.

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UART LIN Mode Counter Register

Figure 16-52 LINCNT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R/W-0h R/W-0h
Table 16-50 LINCNT Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R/W 0h
15-0 VALUE R/W 0h 16 bit up counter clocked by the functional clock of the UART.
0h = Smallest value
FFFFh = Highest possible value

16.3.38 LINCTL (Offset = 1134h) [Reset = 00000000h]

LINCTL is shown in Figure 16-53 and described in Table 16-51.

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UART LIN Mode Control Register

Figure 16-53 LINCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED LINC0_MATCH LINC1CAP LINC0CAP RESERVED CNTRXLOW ZERONE CTRENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 16-51 LINCTL Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R/W 0h
6 LINC0_MATCH R/W 0h Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled.
0h = Counter compare match mode disabled (capture mode enabled)
1h = Counter compare match enabled (capture mode disabled)
5 LINC1CAP R/W 0h Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled.
0h = Capture counter on positive UARTxRXD edge disabled
1h = Capture counter on positive UARTxRXD edge enabled
4 LINC0CAP R/W 0h Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled.
0h = Capture counter on negative UARTxRXD edge disabled
1h = Capture counter on negative UARTxRXD edge enabled
3 RESERVED R/W 0h
2 CNTRXLOW R/W 0h Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments.
0h = Count while low Signal on UARTxRXD disabled
1h = Count while low Signal on UARTxRXD enabled
1 ZERONE R/W 0h Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD
0h = Zero on negative edge disabled
1h = Zero on negative edge enabled
0 CTRENA R/W 0h LIN Counter Enable. LIN counter will only count when enabled.
0h = Counter disabled
1h = Counter enabled

16.3.39 LINC0 (Offset = 1138h) [Reset = 00000000h]

LINC0 is shown in Figure 16-54 and described in Table 16-52.

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UART LIN Mode Capture 0 Register

Figure 16-54 LINC0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R/W-0h R/W-0h
Table 16-52 LINC0 Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R/W 0h
15-0 DATA R/W 0h 16 Bit Capture / Compare Register
Captures current LINCTR value on RXD falling edge and can generate a LINC0 interrupt when capture is enabled (LINC0CAP = 1).

If compare mode is enabled (LINC0_MATCH = 1), a counter match can generate a LINC0 interrupt.
0h = Smallest value
FFFFh = Highest possible value

16.3.40 LINC1 (Offset = 113Ch) [Reset = 00000000h]

LINC1 is shown in Figure 16-55 and described in Table 16-53.

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UART LIN Mode Capture 1 Register

Figure 16-55 LINC1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R/W-0h R/W-0h
Table 16-53 LINC1 Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R/W 0h
15-0 DATA R/W 0h 16 Bit Capture / Compare Register
Captures current LINCTR value on RXD rising edge and can generate a LINC1 interrupt when capture is enabled (LINC1CAP = 1)
0h = Smallest value
FFFFh = Highest possible value

16.3.41 IRCTL (Offset = 1140h) [Reset = X]

IRCTL is shown in Figure 16-56 and described in Table 16-54.

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IrDA Control Register

Figure 16-56 IRCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED IRRXPL RESERVED
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
IRTXPL IRTXCLK IREN
R/W-0h R/W-0h R/W-0h
Table 16-54 IRCTL Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R/W 0h
9 IRRXPL R/W 0h IrDA receive input UCAxRXD polarity
0h = HIGH : IrDA transceiver delivers a high pulse when a light pulse is seen
1h = LOW : IrDA transceiver delivers a low pulse when a light pulse is seen
8 RESERVED R/W 0h
7-2 IRTXPL R/W 0h Transmit pulse length.
Pulse length t(PULSE) = (IRTXPLx + 1) / [2 * f(IRTXCLK)]
(IRTXCLK = functional clock of the UART)
0h = Smallest value
3Fh = Highest possible value
1 IRTXCLK R/W 0h IrDA transmit pulse clock select
0h (R/W) = IrDA encode data is based on the functional clock.
1h (R/W) = IrDA encode data is based on the Baud Rate clock<
when select 8x oversampling, the IRTXPL cycle should less 8;
when select 16x oversampling, the IRTXPL cycle should less 16.
0 IREN R/W 0h IrDA encoder/decoder enable
0h (R/W) = IrDA encoder/decoder disabled
1h (R/W) = IrDA encoder/decoder enabled

16.3.42 AMASK (Offset = 1148h) [Reset = 000000FFh]

AMASK is shown in Figure 16-57 and described in Table 16-55.

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Self Address Mask Register The AMASK register is used to enable the address mask for 9-bit or Idle-Line mode. The address bits are masked to create a set of addresses to be matched with the received address byte.
Used in DALI, UART 9-Bit or Idle-Line mode.

Figure 16-57 AMASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R/W-0h R/W-FFh
Table 16-55 AMASK Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R/W 0h
7-0 VALUE R/W FFh Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UARTxADDR register must match.
0h = Smallest value
FFh = Highest possible value

16.3.43 ADDR (Offset = 114Ch) [Reset = 00000000h]

ADDR is shown in Figure 16-58 and described in Table 16-56.

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Self Address Register The ADDR register is used to write the specific address that should be matched with the receiving byte when the Address Mask (AMASK) is set to FFh. This register is used in conjunction with AMASK to form a match for address-byte received.
Used in DALI, UART 9-Bit or Idle-Line mode.

Figure 16-58 ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALUE
R/W-0h R/W-0h
Table 16-56 ADDR Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R/W 0h
7-0 VALUE R/W 0h Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh.
0h = Smallest value
FFh = Highest possible value

16.3.44 CLKDIV2 (Offset = 1160h) [Reset = 00000000h]

CLKDIV2 is shown in Figure 16-59 and described in Table 16-57.

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This register is used to specify module-specific divide ratio of the functional clock.
(Only in UART extended)

Figure 16-59 CLKDIV2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RATIO
R/W-0h R/W-0h
Table 16-57 CLKDIV2 Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R/W 0h
2-0 RATIO R/W 0h Selects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8