SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

9.3 GPIO Registers

Table 9-2 lists the memory-mapped registers for the GPIO registers. All register offset addresses not listed in Table 9-2 should be considered as reserved locations and the register contents should not be modified.

Table 9-2 GPIO Registers
OffsetAcronymRegister NameGroupSection
400hFSUB_0Subsciber Port 0Go
404hFSUB_1Subscriber Port 1Go
444hFPUB_0Publisher Port 0Go
448hFPUB_1Publisher Port 1Go
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1010hCLKOVRClock OverrideGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt indexGEN_EVENT0Go
1058hIMASKInterrupt maskGEN_EVENT0Go
1060hRISRaw interrupt statusGEN_EVENT0Go
1068hMISMasked interrupt statusGEN_EVENT0Go
1070hISETInterrupt setGEN_EVENT0Go
1078hICLRInterrupt clearGEN_EVENT0Go
1080hIIDXInterrupt indexGEN_EVENT1Go
1088hIMASKInterrupt maskGEN_EVENT1Go
1090hRISRaw interrupt statusGEN_EVENT1Go
1098hMISMasked interrupt statusGEN_EVENT1Go
10A0hISETInterrupt setGEN_EVENT1Go
10A8hICLRInterrupt clearGEN_EVENT1Go
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1200hDOUT3_0Data output 3 to 0Go
1204hDOUT7_4Data output 7 to 4Go
1208hDOUT11_8Data output 11 to 8Go
120ChDOUT15_12Data output 15 to 12Go
1210hDOUT19_16Data output 19 to 16Go
1214hDOUT23_20Data output 23 to 20Go
1218hDOUT27_24Data output 27 to 24Go
121ChDOUT31_28Data output 31 to 28Go
1280hDOUT31_0Data output 31 to 0Go
1290hDOUTSET31_0Data output set 31 to 0Go
12A0hDOUTCLR31_0Data output clear 31 to 0Go
12B0hDOUTTGL31_0Data output toggle 31 to 0Go
12C0hDOE31_0Data output enable 31 to 0Go
12D0hDOESET31_0Data output enable set 31 to 0Go
12E0hDOECLR31_0Data output enable clear 31 to 0Go
1300hDIN3_0Data input 3 to 0Go
1304hDIN7_4Data input 7 to 4Go
1308hDIN11_8Data input 11 to 8Go
130ChDIN15_12Data input 15 to 12Go
1310hDIN19_16Data input 19 to 16Go
1314hDIN23_20Data input 23 to 20Go
1318hDIN27_24Data input 27 to 24Go
131ChDIN31_28Data input 31 to 28Go
1380hDIN31_0Data input 31 to 0Go
1390hPOLARITY15_0Polarity 15 to 0Go
13A0hPOLARITY31_16Polarity 31 to 16Go
1400hCTLFAST WAKE GLOBAL ENGo
1404hFASTWAKEFAST WAKE ENABLEGo
1500hSUB0CFGSubscriber 0 configurationGo
1508hFILTEREN15_0Filter Enable 15 to 0Go
150ChFILTEREN31_16Filter Enable 31 to 16Go
1510hDMAMASKDMA Write MASKGo
1520hSUB1CFGSubscriber 1 configurationGo

Complex bit access types are encoded to fit into small table cells. Table 9-3 shows the codes that are used for access types in this section.

Table 9-3 GPIO Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
KKWrite protected by a key
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

9.3.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 9-4 and described in Table 9-4.

Return to the Summary Table.

Subscriber port

Figure 9-4 FSUB_0
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 9-4 FSUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

9.3.2 FSUB_1 (Offset = 404h) [Reset = 00000000h]

FSUB_1 is shown in Figure 9-5 and described in Table 9-5.

Return to the Summary Table.

Subscriber port

Figure 9-5 FSUB_1
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 9-5 FSUB_1 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

9.3.3 FPUB_0 (Offset = 444h) [Reset = 00000000h]

FPUB_0 is shown in Figure 9-6 and described in Table 9-6.

Return to the Summary Table.

Publisher port

Figure 9-6 FPUB_0
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 9-6 FPUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

9.3.4 FPUB_1 (Offset = 448h) [Reset = 00000000h]

FPUB_1 is shown in Figure 9-7 and described in Table 9-7.

Return to the Summary Table.

Publisher port

Figure 9-7 FPUB_1
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 9-7 FPUB_1 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

9.3.5 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 9-8 and described in Table 9-8.

Return to the Summary Table.

Register to control the power state

Figure 9-8 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDENABLE
R/W-K-0h
Table 9-8 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLEK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

9.3.6 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 9-9 and described in Table 9-9.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 9-9 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-
15141312111098
RESERVED
W-
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-WK-0hWK-0h
Table 9-9 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

9.3.7 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 9-10 and described in Table 9-10.

Return to the Summary Table.

peripheral enable and reset status

Figure 9-10 STAT
3130292827262524
RESERVED
R-
2322212019181716
RESERVEDRESETSTKY
R-R-0h
15141312111098
RESERVED
R-
76543210
RESERVED
R-
Table 9-10 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

9.3.8 CLKOVR (Offset = 1010h) [Reset = 00000000h]

CLKOVR is shown in Figure 9-11 and described in Table 9-11.

Return to the Summary Table.

This register overrides the functional clock request by this peripheral to the system

Figure 9-11 CLKOVR
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRUN_STOPOVERRIDE
R/W-0hR/W-0hR/W-0h
Table 9-11 CLKOVR Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1RUN_STOPR/W0hIf OVERRIDE is enabled, this register is used to manually control the peripheral's clock request to the system
0h = Run/ungate functional clock
1h = Stop/gate functional clock
0OVERRIDER/W0hUnlocks the functionality of RUN_STOP to override the automatic peripheral clock request
0h = Override disabled
1h = Override enabled

9.3.9 PDBGCTL (Offset = 1018h) [Reset = 00000001h]

PDBGCTL is shown in Figure 9-12 and described in Table 9-12.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 9-12 PDBGCTL
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDFREE
R/W-0hR/W-1h
Table 9-12 PDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

9.3.10 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 9-13 and described in Table 9-13.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 9-13 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 9-13 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
0h = No bit is set means there is no pending interrupt request
1h = DIO0 interrupt
2h = DIO1 interrupt
3h = DIO2 interrupt
4h = DIO3 interrupt
5h = DIO4 interrupt
6h = DIO5 interrupt
7h = DIO6 interrupt
8h = DIO7 interrupt
9h = DIO8 interrupt
Ah = DIO9 interrupt
Bh = DIO10 interrupt
Ch = DIO11 interrupt
Dh = DIO12 interrupt
Eh = DIO13 interrupt
Fh = DIO14 interrupt
10h = DIO15 interrupt
11h = DIO16 interrupt
12h = DIO17 interrupt
13h = DIO18 interrupt
14h = DIO19 interrupt
15h = DIO20 interrupt
16h = DIO21 interrupt
17h = DIO22 interrupt
18h = DIO23 interrupt
19h = DIO24 interrupt
1Ah = DIO25 interrupt
1Bh = DIO26 interrupt
1Ch = DIO27 interrupt
1Dh = DIO28 interrupt
1Eh = DIO29 interrupt
1Fh = DIO30 interrupt
20h = DIO31 interrupt

9.3.11 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 9-14 and described in Table 9-14.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-14 IMASK
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-14 IMASK Field Descriptions
BitFieldTypeResetDescription
31DIO31R/W0hDIO31 event mask
0h = Event is masked
1h = Event is unmasked
30DIO30R/W0hDIO30 event mask
0h = Event is masked
1h = Event is unmasked
29DIO29R/W0hDIO29 event mask
0h = Event is masked
1h = Event is unmasked
28DIO28R/W0hDIO28 event mask
0h = Event is masked
1h = Event is unmasked
27DIO27R/W0hDIO27 event mask
0h = Event is masked
1h = Event is unmasked
26DIO26R/W0hDIO26 event mask
0h = Event is masked
1h = Event is unmasked
25DIO25R/W0hDIO25 event mask
0h = Event is masked
1h = Event is unmasked
24DIO24R/W0hDIO24 event mask
0h = Event is masked
1h = Event is unmasked
23DIO23R/W0hDIO23 event mask
0h = Event is masked
1h = Event is unmasked
22DIO22R/W0hDIO22 event mask
0h = Event is masked
1h = Event is unmasked
21DIO21R/W0hDIO21 event mask
0h = Event is masked
1h = Event is unmasked
20DIO20R/W0hDIO20 event mask
0h = Event is masked
1h = Event is unmasked
19DIO19R/W0hDIO19 event mask
0h = Event is masked
1h = Event is unmasked
18DIO18R/W0hDIO18 event mask
0h = Event is masked
1h = Event is unmasked
17DIO17R/W0hDIO17 event mask
0h = Event is masked
1h = Event is unmasked
16DIO16R/W0hDIO16 event mask
0h = Event is masked
1h = Event is unmasked
15DIO15R/W0hDIO15 event mask
0h = Event is masked
1h = Event is unmasked
14DIO14R/W0hDIO14 event mask
0h = Event is masked
1h = Event is unmasked
13DIO13R/W0hDIO13 event mask
0h = Event is masked
1h = Event is unmasked
12DIO12R/W0hDIO12 event mask
0h = Event is masked
1h = Event is unmasked
11DIO11R/W0hDIO11 event mask
0h = Event is masked
1h = Event is unmasked
10DIO10R/W0hDIO10 event mask
0h = Event is masked
1h = Event is unmasked
9DIO9R/W0hDIO9 event mask
0h = Event is masked
1h = Event is unmasked
8DIO8R/W0hDIO8 event mask
0h = Event is masked
1h = Event is unmasked
7DIO7R/W0hDIO7 event mask
0h = Event is masked
1h = Event is unmasked
6DIO6R/W0hDIO6 event mask
0h = Event is masked
1h = Event is unmasked
5DIO5R/W0hDIO5 event mask
0h = Event is masked
1h = Event is unmasked
4DIO4R/W0hDIO4 event mask
0h = Event is masked
1h = Event is unmasked
3DIO3R/W0hDIO3 event mask
0h = Event is masked
1h = Event is unmasked
2DIO2R/W0hDIO2 event mask
0h = Event is masked
1h = Event is unmasked
1DIO1R/W0hDIO1 event mask
0h = Event is masked
1h = Event is unmasked
0DIO0R/W0hDIO0 event mask
0h = Event is masked
1h = Event is unmasked

9.3.12 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 9-15 and described in Table 9-15.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-15 RIS
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-15 RIS Field Descriptions
BitFieldTypeResetDescription
31DIO31R0hDIO31 event
0h = DIO31 event did not occur
1h = DIO31 event occurred
30DIO30R0hDIO30 event
0h = DIO30 event did not occur
1h = DIO30 event occurred
29DIO29R0hDIO29 event
0h = DIO29 event did not occur
1h = DIO29 event occurred
28DIO28R0hDIO28 event
0h = DIO28 event did not occur
1h = DIO28 event occurred
27DIO27R0hDIO27 event
0h = DIO27 event did not occur
1h = DIO27 event occurred
26DIO26R0hDIO26 event
0h = DIO26 event did not occur
1h = DIO26 event occurred
25DIO25R0hDIO25 event
0h = DIO25 event did not occur
1h = DIO25 event occurred
24DIO24R0hDIO24 event
0h = DIO24 event did not occur
1h = DIO24 event occurred
23DIO23R0hDIO23 event
0h = DIO23 event did not occur
1h = DIO23 event occurred
22DIO22R0hDIO22 event
0h = DIO22 event did not occur
1h = DIO22 event occurred
21DIO21R0hDIO21 event
0h = DIO21 event did not occur
1h = DIO21 event occurred
20DIO20R0hDIO20 event
0h = DIO20 event did not occur
1h = DIO20 event occurred
19DIO19R0hDIO19 event
0h = DIO19 event did not occur
1h = DIO19 event occurred
18DIO18R0hDIO18 event
0h = DIO18 event did not occur
1h = DIO18 event occurred
17DIO17R0hDIO17 event
0h = DIO17 event did not occur
1h = DIO17 event occurred
16DIO16R0hDIO16 event
0h = DIO16 event did not occur
1h = DIO16 event occurred
15DIO15R0hDIO15 event
0h = DIO15 event did not occur
1h = DIO15 event occurred
14DIO14R0hDIO14 event
0h = DIO14 event did not occur
1h = DIO14 event occurred
13DIO13R0hDIO13 event
0h = DIO13 event did not occur
1h = DIO13 event occurred
12DIO12R0hDIO12 event
0h = DIO12 event did not occur
1h = DIO12 event occurred
11DIO11R0hDIO11 event
0h = DIO11 event did not occur
1h = DIO11 event occurred
10DIO10R0hDIO10 event
0h = DIO10 event did not occur
1h = DIO10 event occurred
9DIO9R0hDIO9 event
0h = DIO9 event did not occur
1h = DIO9 event occurred
8DIO8R0hDIO8 event
0h = DIO8 event did not occur
1h = DIO8 event occurred
7DIO7R0hDIO7 event
0h = DIO7 event did not occur
1h = DIO7 event occurred
6DIO6R0hDIO6 event
0h = DIO6 event did not occur
1h = DIO6 event occurred
5DIO5R0hDIO5 event
0h = DIO5 event did not occur
1h = DIO5 event occurred
4DIO4R0hDIO4 event
0h = DIO4 event did not occur
1h = DIO4 event occurred
3DIO3R0hDIO3 event
0h = DIO3 event did not occur
1h = DIO3 event occurred
2DIO2R0hDIO2 event
0h = DIO2 event did not occur
1h = DIO2 event occurred
1DIO1R0hDIO1 event
0h = DIO1 event did not occur
1h = DIO1 event occurred
0DIO0R0hDIO0 event
0h = DIO0 event did not occur
1h = DIO0 event occurred

9.3.13 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 9-16 and described in Table 9-16.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-16 MIS
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-16 MIS Field Descriptions
BitFieldTypeResetDescription
31DIO31R0hDIO31 event
0h = DIO31 event did not occur
1h = DIO31 event occurred
30DIO30R0hDIO30 event
0h = DIO30 event did not occur
1h = DIO30 event occurred
29DIO29R0hDIO29 event
0h = DIO29 event did not occur
1h = DIO29 event occurred
28DIO28R0hDIO28 event
0h = DIO28 event did not occur
1h = DIO28 event occurred
27DIO27R0hDIO27 event
0h = DIO27 event did not occur
1h = DIO27 event occurred
26DIO26R0hDIO26 event
0h = DIO26 event did not occur
1h = DIO26 event occurred
25DIO25R0hDIO25 event
0h = DIO25 event did not occur
1h = DIO25 event occurred
24DIO24R0hDIO24 event
0h = DIO24 event did not occur
1h = DIO24 event occurred
23DIO23R0hDIO23 event
0h = DIO23 event did not occur
1h = DIO23 event occurred
22DIO22R0hDIO22 event
0h = DIO22 event did not occur
1h = DIO22 event occurred
21DIO21R0hDIO21 event
0h = DIO21 event did not occur
1h = DIO21 event occurred
20DIO20R0hDIO20 event
0h = DIO20 event did not occur
1h = DIO20 event occurred
19DIO19R0hDIO19 event
0h = DIO19 event did not occur
1h = DIO19 event occurred
18DIO18R0hDIO18 event
0h = DIO18 event did not occur
1h = DIO18 event occurred
17DIO17R0hDIO17 event
0h = DIO17 event did not occur
1h = DIO17 event occurred
16DIO16R0hDIO16 event
0h = DIO16 event did not occur
1h = DIO16 event occurred
15DIO15R0hDIO15 event
0h = DIO15 event did not occur
1h = DIO15 event occurred
14DIO14R0hDIO14 event
0h = DIO14 event did not occur
1h = DIO14 event occurred
13DIO13R0hDIO13 event
0h = DIO13 event did not occur
1h = DIO13 event occurred
12DIO12R0hDIO12 event
0h = DIO12 event did not occur
1h = DIO12 event occurred
11DIO11R0hDIO11 event
0h = DIO11 event did not occur
1h = DIO11 event occurred
10DIO10R0hDIO10 event
0h = DIO10 event did not occur
1h = DIO10 event occurred
9DIO9R0hDIO9 event
0h = DIO9 event did not occur
1h = DIO9 event occurred
8DIO8R0hDIO8 event
0h = DIO8 event did not occur
1h = DIO8 event occurred
7DIO7R0hDIO7 event
0h = DIO7 event did not occur
1h = DIO7 event occurred
6DIO6R0hDIO6 event
0h = DIO6 event did not occur
1h = DIO6 event occurred
5DIO5R0hDIO5 event
0h = DIO5 event did not occur
1h = DIO5 event occurred
4DIO4R0hDIO4 event
0h = DIO4 event did not occur
1h = DIO4 event occurred
3DIO3R0hDIO3 event
0h = DIO3 event did not occur
1h = DIO3 event occurred
2DIO2R0hDIO2 event
0h = DIO2 event did not occur
1h = DIO2 event occurred
1DIO1R0hDIO1 event
0h = DIO1 event did not occur
1h = DIO1 event occurred
0DIO0R0hDIO0 event
0h = DIO0 event did not occur
1h = DIO0 event occurred

9.3.14 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 9-17 and described in Table 9-17.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-17 ISET
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-17 ISET Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hDIO31 event
0h = No effect
1h = Sets DIO31 in RIS register
30DIO30W0hDIO30 event
0h = No effect
1h = Sets DIO30 in RIS register
29DIO29W0hDIO29 event
0h = No effect
1h = Sets DIO29 in RIS register
28DIO28W0hDIO28 event
0h = No effect
1h = Sets DIO28 in RIS register
27DIO27W0hDIO27 event
0h = No effect
1h = Sets DIO27 in RIS register
26DIO26W0hDIO26 event
0h = No effect
1h = Sets DIO26 in RIS register
25DIO25W0hDIO25 event
0h = No effect
1h = Sets DIO25 in RIS register
24DIO24W0hDIO24 event
0h = No effect
1h = Sets DIO24 in RIS register
23DIO23W0hDIO23 event
0h = No effect
1h = Sets DIO23 in RIS register
22DIO22W0hDIO22 event
0h = No effect
1h = Sets DIO22 in RIS register
21DIO21W0hDIO21 event
0h = No effect
1h = Sets DIO21 in RIS register
20DIO20W0hDIO20 event
0h = No effect
1h = Sets DIO20 in RIS register
19DIO19W0hDIO19 event
0h = No effect
1h = Sets DIO19 in RIS register
18DIO18W0hDIO18 event
0h = No effect
1h = Sets DIO18 in RIS register
17DIO17W0hDIO17 event
0h = No effect
1h = Sets DIO17 in RIS register
16DIO16W0hDIO16 event
0h = No effect
1h = Sets DIO16 in RIS register
15DIO15W0hDIO15 event
0h = No effect
1h = Sets DIO15 in RIS register
14DIO14W0hDIO14 event
0h = No effect
1h = Sets DIO14 in RIS register
13DIO13W0hDIO13 event
0h = No effect
1h = Sets DIO13 in RIS register
12DIO12W0hDIO12 event
0h = No effect
1h = Sets DIO12 in RIS register
11DIO11W0hDIO11 event
0h = No effect
1h = Sets DIO11 in RIS register
10DIO10W0hDIO10 event
0h = No effect
1h = Sets DIO10 in RIS register
9DIO9W0hDIO9 event
0h = No effect
1h = Sets DIO9 in RIS register
8DIO8W0hDIO8 event
0h = No effect
1h = Sets DIO8 in RIS register
7DIO7W0hDIO7 event
0h = No effect
1h = Sets DIO7 in RIS register
6DIO6W0hDIO6 event
0h = No effect
1h = Sets DIO6 in RIS register
5DIO5W0hDIO5 event
0h = No effect
1h = Sets DIO5 in RIS register
4DIO4W0hDIO4 event
0h = No effect
1h = Sets DIO4 in RIS register
3DIO3W0hDIO3 event
0h = No effect
1h = Sets DIO3 in RIS register
2DIO2W0hDIO2 event
0h = No effect
1h = Sets DIO2 in RIS register
1DIO1W0hDIO1 event
0h = No effect
1h = Sets DIO1 in RIS register
0DIO0W0hDIO0 event
0h = No effect
1h = Sets DIO0 in RIS register

9.3.15 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 9-18 and described in Table 9-18.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-18 ICLR
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-18 ICLR Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hDIO31 event
0h = No effect
1h = Clears DIO31 in RIS register
30DIO30W0hDIO30 event
0h = No effect
1h = Clears DIO30 in RIS register
29DIO29W0hDIO29 event
0h = No effect
1h = Clears DIO29 in RIS register
28DIO28W0hDIO28 event
0h = No effect
1h = Clears DIO28 in RIS register
27DIO27W0hDIO27 event
0h = No effect
1h = Clears DIO27 in RIS register
26DIO26W0hDIO26 event
0h = No effect
1h = Clears DIO26 in RIS register
25DIO25W0hDIO25 event
0h = No effect
1h = Clears DIO25 in RIS register
24DIO24W0hDIO24 event
0h = No effect
1h = Clears DIO24 in RIS register
23DIO23W0hDIO23 event
0h = No effect
1h = Clears DIO23 in RIS register
22DIO22W0hDIO22 event
0h = No effect
1h = Clears DIO22 in RIS register
21DIO21W0hDIO21 event
0h = No effect
1h = Clears DIO21 in RIS register
20DIO20W0hDIO20 event
0h = No effect
1h = Clears DIO20 in RIS register
19DIO19W0hDIO19 event
0h = No effect
1h = Clears DIO19 in RIS register
18DIO18W0hDIO18 event
0h = No effect
1h = Clears DIO18 in RIS register
17DIO17W0hDIO17 event
0h = No effect
1h = Clears DIO17 in RIS register
16DIO16W0hDIO16 event
0h = No effect
1h = Clears DIO16 in RIS register
15DIO15W0hDIO15 event
0h = No effect
1h = Clears DIO15 in RIS register
14DIO14W0hDIO14 event
0h = No effect
1h = Clears DIO14 in RIS register
13DIO13W0hDIO13 event
0h = No effect
1h = Clears DIO13 in RIS register
12DIO12W0hDIO12 event
0h = No effect
1h = Clears DIO12 in RIS register
11DIO11W0hDIO11 event
0h = No effect
1h = Clears DIO11 in RIS register
10DIO10W0hDIO10 event
0h = No effect
1h = Clears DIO10 in RIS register
9DIO9W0hDIO9 event
0h = No effect
1h = Clears DIO9 in RIS register
8DIO8W0hDIO8 event
0h = No effect
1h = Clears DIO8 in RIS register
7DIO7W0hDIO7 event
0h = No effect
1h = Clears DIO7 in RIS register
6DIO6W0hDIO6 event
0h = No effect
1h = Clears DIO6 in RIS register
5DIO5W0hDIO5 event
0h = No effect
1h = Clears DIO5 in RIS register
4DIO4W0hDIO4 event
0h = No effect
1h = Clears DIO4 in RIS register
3DIO3W0hDIO3 event
0h = No effect
1h = Clears DIO3 in RIS register
2DIO2W0hDIO2 event
0h = No effect
1h = Clears DIO2 in RIS register
1DIO1W0hDIO1 event
0h = No effect
1h = Clears DIO1 in RIS register
0DIO0W0hDIO0 event
0h = No effect
1h = Clears DIO0 in RIS register

9.3.16 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 9-19 and described in Table 9-19.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 9-19 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 9-19 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
0h = No bit is set means there is no pending interrupt request
1h = DIO0 interrupt
2h = DIO1 interrupt
3h = DIO2 interrupt
4h = DIO3 interrupt
5h = DIO4 interrupt
6h = DIO5 interrupt
7h = DIO6 interrupt
8h = DIO7 interrupt
9h = DIO8 interrupt
Ah = DIO9 interrupt
Bh = DIO10 interrupt
Ch = DIO11 interrupt
Dh = DIO12 interrupt
Eh = DIO13 interrupt
Fh = DIO14 interrupt
10h = DIO15 interrupt

9.3.17 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 9-20 and described in Table 9-20.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-20 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-20 IMASK Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15DIO15R/W0hDIO15 event mask
0h = Event is masked
1h = Event is unmasked
14DIO14R/W0hDIO14 event mask
0h = Event is masked
1h = Event is unmasked
13DIO13R/W0hDIO13 event mask
0h = Event is masked
1h = Event is unmasked
12DIO12R/W0hDIO12 event mask
0h = Event is masked
1h = Event is unmasked
11DIO11R/W0hDIO11 event mask
0h = Event is masked
1h = Event is unmasked
10DIO10R/W0hDIO10 event mask
0h = Event is masked
1h = Event is unmasked
9DIO9R/W0hDIO9 event mask
0h = Event is masked
1h = Event is unmasked
8DIO8R/W0hDIO8 event mask
0h = Event is masked
1h = Event is unmasked
7DIO7R/W0hDIO7 event mask
0h = Event is masked
1h = Event is unmasked
6DIO6R/W0hDIO6 event mask
0h = Event is masked
1h = Event is unmasked
5DIO5R/W0hDIO5 event mask
0h = Event is masked
1h = Event is unmasked
4DIO4R/W0hDIO4 event mask
0h = Event is masked
1h = Event is unmasked
3DIO3R/W0hDIO3 event mask
0h = Event is masked
1h = Event is unmasked
2DIO2R/W0hDIO2 event mask
0h = Event is masked
1h = Event is unmasked
1DIO1R/W0hDIO1 event mask
0h = Event is masked
1h = Event is unmasked
0DIO0R/W0hDIO0 event mask
0h = Event is masked
1h = Event is unmasked

9.3.18 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 9-21 and described in Table 9-21.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-21 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-21 RIS Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15DIO15R0hDIO15 event
0h = DIO15 event did not occur
1h = DIO15 event occurred
14DIO14R0hDIO14 event
0h = DIO14 event did not occur
1h = DIO14 event occurred
13DIO13R0hDIO13 event
0h = DIO13 event did not occur
1h = DIO13 event occurred
12DIO12R0hDIO12 event
0h = DIO12 event did not occur
1h = DIO12 event occurred
11DIO11R0hDIO11 event
0h = DIO11 event did not occur
1h = DIO11 event occurred
10DIO10R0hDIO10 event
0h = DIO10 event did not occur
1h = DIO10 event occurred
9DIO9R0hDIO9 event
0h = DIO9 event did not occur
1h = DIO9 event occurred
8DIO8R0hDIO8 event
0h = DIO8 event did not occur
1h = DIO8 event occurred
7DIO7R0hDIO7 event
0h = DIO7 event did not occur
1h = DIO7 event occurred
6DIO6R0hDIO6 event
0h = DIO6 event did not occur
1h = DIO6 event occurred
5DIO5R0hDIO5 event
0h = DIO5 event did not occur
1h = DIO5 event occurred
4DIO4R0hDIO4 event
0h = DIO4 event did not occur
1h = DIO4 event occurred
3DIO3R0hDIO3 event
0h = DIO3 event did not occur
1h = DIO3 event occurred
2DIO2R0hDIO2 event
0h = DIO2 event did not occur
1h = DIO2 event occurred
1DIO1R0hDIO1 event
0h = DIO1 event did not occur
1h = DIO1 event occurred
0DIO0R0hDIO0 event
0h = DIO0 event did not occur
1h = DIO0 event occurred

9.3.19 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 9-22 and described in Table 9-22.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-22 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-22 MIS Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15DIO15R0hDIO15 event
0h = DIO15 event did not occur
1h = DIO15 event occurred
14DIO14R0hDIO14 event
0h = DIO14 event did not occur
1h = DIO14 event occurred
13DIO13R0hDIO13 event
0h = DIO13 event did not occur
1h = DIO13 event occurred
12DIO12R0hDIO12 event
0h = DIO12 event did not occur
1h = DIO12 event occurred
11DIO11R0hDIO11 event
0h = DIO11 event did not occur
1h = DIO11 event occurred
10DIO10R0hDIO10 event
0h = DIO10 event did not occur
1h = DIO10 event occurred
9DIO9R0hDIO9 event
0h = DIO9 event did not occur
1h = DIO9 event occurred
8DIO8R0hDIO8 event
0h = DIO8 event did not occur
1h = DIO8 event occurred
7DIO7R0hDIO7 event
0h = DIO7 event did not occur
1h = DIO7 event occurred
6DIO6R0hDIO6 event
0h = DIO6 event did not occur
1h = DIO6 event occurred
5DIO5R0hDIO5 event
0h = DIO5 event did not occur
1h = DIO5 event occurred
4DIO4R0hDIO4 event
0h = DIO4 event did not occur
1h = DIO4 event occurred
3DIO3R0hDIO3 event
0h = DIO3 event did not occur
1h = DIO3 event occurred
2DIO2R0hDIO2 event
0h = DIO2 event did not occur
1h = DIO2 event occurred
1DIO1R0hDIO1 event
0h = DIO1 event did not occur
1h = DIO1 event occurred
0DIO0R0hDIO0 event
0h = DIO0 event did not occur
1h = DIO0 event occurred

9.3.20 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 9-23 and described in Table 9-23.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-23 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-23 ISET Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDW0h
15DIO15W0hDIO15 event
0h = No effect
1h = Sets DIO15 in RIS register
14DIO14W0hDIO14 event
0h = No effect
1h = Sets DIO14 in RIS register
13DIO13W0hDIO13 event
0h = No effect
1h = Sets DIO13 in RIS register
12DIO12W0hDIO12 event
0h = No effect
1h = Sets DIO12 in RIS register
11DIO11W0hDIO11 event
0h = No effect
1h = Sets DIO11 in RIS register
10DIO10W0hDIO10 event
0h = No effect
1h = Sets DIO10 in RIS register
9DIO9W0hDIO9 event
0h = No effect
1h = Sets DIO9 in RIS register
8DIO8W0hDIO8 event
0h = No effect
1h = Sets DIO8 in RIS register
7DIO7W0hDIO7 event
0h = No effect
1h = Sets DIO7 in RIS register
6DIO6W0hDIO6 event
0h = No effect
1h = Sets DIO6 in RIS register
5DIO5W0hDIO5 event
0h = No effect
1h = Sets DIO5 in RIS register
4DIO4W0hDIO4 event
0h = No effect
1h = Sets DIO4 in RIS register
3DIO3W0hDIO3 event
0h = No effect
1h = Sets DIO3 in RIS register
2DIO2W0hDIO2 event
0h = No effect
1h = Sets DIO2 in RIS register
1DIO1W0hDIO1 event
0h = No effect
1h = Sets DIO1 in RIS register
0DIO0W0hDIO0 event
0h = No effect
1h = Sets DIO0 in RIS register

9.3.21 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 9-24 and described in Table 9-24.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-24 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-24 ICLR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDW0h
15DIO15W0hDIO15 event
0h = No effect
1h = Clears DIO15 in RIS register
14DIO14W0hDIO14 event
0h = No effect
1h = Clears DIO14 in RIS register
13DIO13W0hDIO13 event
0h = No effect
1h = Clears DIO13 in RIS register
12DIO12W0hDIO12 event
0h = No effect
1h = Clears DIO12 in RIS register
11DIO11W0hDIO11 event
0h = No effect
1h = Clears DIO11 in RIS register
10DIO10W0hDIO10 event
0h = No effect
1h = Clears DIO10 in RIS register
9DIO9W0hDIO9 event
0h = No effect
1h = Clears DIO9 in RIS register
8DIO8W0hDIO8 event
0h = No effect
1h = Clears DIO8 in RIS register
7DIO7W0hDIO7 event
0h = No effect
1h = Clears DIO7 in RIS register
6DIO6W0hDIO6 event
0h = No effect
1h = Clears DIO6 in RIS register
5DIO5W0hDIO5 event
0h = No effect
1h = Clears DIO5 in RIS register
4DIO4W0hDIO4 event
0h = No effect
1h = Clears DIO4 in RIS register
3DIO3W0hDIO3 event
0h = No effect
1h = Clears DIO3 in RIS register
2DIO2W0hDIO2 event
0h = No effect
1h = Clears DIO2 in RIS register
1DIO1W0hDIO1 event
0h = No effect
1h = Clears DIO1 in RIS register
0DIO0W0hDIO0 event
0h = No effect
1h = Clears DIO0 in RIS register

9.3.22 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 9-25 and described in Table 9-25.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 9-25 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 9-25 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
0h = No bit is set means there is no pending interrupt request
1h = DIO0 interrupt
2h = DIO1 interrupt
3h = DIO2 interrupt
4h = DIO3 interrupt
5h = DIO4 interrupt
6h = DIO5 interrupt
7h = DIO6 interrupt
8h = DIO7 interrupt
9h = DIO8 interrupt
Ah = DIO9 interrupt
Bh = DIO10 interrupt
Ch = DIO11 interrupt
Dh = DIO12 interrupt
Eh = DIO13 interrupt
Fh = DIO14 interrupt
10h = DIO15 interrupt

9.3.23 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 9-26 and described in Table 9-26.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 9-26 IMASK
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 9-26 IMASK Field Descriptions
BitFieldTypeResetDescription
31DIO31R/W0hDIO31 event mask
0h = Event is masked
1h = Event is unmasked
30DIO30R/W0hDIO30 event mask
0h = Event is masked
1h = Event is unmasked
29DIO29R/W0hDIO29 event mask
0h = Event is masked
1h = Event is unmasked
28DIO28R/W0hDIO28 event mask
0h = Event is masked
1h = Event is unmasked
27DIO27R/W0hDIO27 event mask
0h = Event is masked
1h = Event is unmasked
26DIO26R/W0hDIO26 event mask
0h = Event is masked
1h = Event is unmasked
25DIO25R/W0hDIO25 event mask
0h = Event is masked
1h = Event is unmasked
24DIO24R/W0hDIO24 event mask
0h = Event is masked
1h = Event is unmasked
23DIO23R/W0hDIO23 event mask
0h = Event is masked
1h = Event is unmasked
22DIO22R/W0hDIO22 event mask
0h = Event is masked
1h = Event is unmasked
21DIO21R/W0hDIO21 event mask
0h = Event is masked
1h = Event is unmasked
20DIO20R/W0hDIO20 event mask
0h = Event is masked
1h = Event is unmasked
19DIO19R/W0hDIO19 event mask
0h = Event is masked
1h = Event is unmasked
18DIO18R/W0hDIO18 event mask
0h = Event is masked
1h = Event is unmasked
17DIO17R/W0hDIO17 event mask
0h = Event is masked
1h = Event is unmasked
16DIO16R/W0hDIO16 event mask
0h = Event is masked
1h = Event is unmasked
15-0RESERVEDR/W0h

9.3.24 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 9-27 and described in Table 9-27.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 9-27 RIS
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 9-27 RIS Field Descriptions
BitFieldTypeResetDescription
31DIO31R0hDIO31 event
0h = DIO31 event did not occur
1h = DIO31 event occurred
30DIO30R0hDIO30 event
0h = DIO30 event did not occur
1h = DIO30 event occurred
29DIO29R0hDIO29 event
0h = DIO29 event did not occur
1h = DIO29 event occurred
28DIO28R0hDIO28 event
0h = DIO28 event did not occur
1h = DIO28 event occurred
27DIO27R0hDIO27 event
0h = DIO27 event did not occur
1h = DIO27 event occurred
26DIO26R0hDIO26 event
0h = DIO26 event did not occur
1h = DIO26 event occurred
25DIO25R0hDIO25 event
0h = DIO25 event did not occur
1h = DIO25 event occurred
24DIO24R0hDIO24 event
0h = DIO24 event did not occur
1h = DIO24 event occurred
23DIO23R0hDIO23 event
0h = DIO23 event did not occur
1h = DIO23 event occurred
22DIO22R0hDIO22 event
0h = DIO22 event did not occur
1h = DIO22 event occurred
21DIO21R0hDIO21 event
0h = DIO21 event did not occur
1h = DIO21 event occurred
20DIO20R0hDIO20 event
0h = DIO20 event did not occur
1h = DIO20 event occurred
19DIO19R0hDIO19 event
0h = DIO19 event did not occur
1h = DIO19 event occurred
18DIO18R0hDIO18 event
0h = DIO18 event did not occur
1h = DIO18 event occurred
17DIO17R0hDIO17 event
0h = DIO17 event did not occur
1h = DIO17 event occurred
16DIO16R0hDIO16 event
0h = DIO16 event did not occur
1h = DIO16 event occurred
15-0RESERVEDR0h

9.3.25 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 9-28 and described in Table 9-28.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 9-28 MIS
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 9-28 MIS Field Descriptions
BitFieldTypeResetDescription
31DIO31R0hDIO31 event
0h = DIO31 event did not occur
1h = DIO31 event occurred
30DIO30R0hDIO30 event
0h = DIO30 event did not occur
1h = DIO30 event occurred
29DIO29R0hDIO29 event
0h = DIO29 event did not occur
1h = DIO29 event occurred
28DIO28R0hDIO28 event
0h = DIO28 event did not occur
1h = DIO28 event occurred
27DIO27R0hDIO27 event
0h = DIO27 event did not occur
1h = DIO27 event occurred
26DIO26R0hDIO26 event
0h = DIO26 event did not occur
1h = DIO26 event occurred
25DIO25R0hDIO25 event
0h = DIO25 event did not occur
1h = DIO25 event occurred
24DIO24R0hDIO24 event
0h = DIO24 event did not occur
1h = DIO24 event occurred
23DIO23R0hDIO23 event
0h = DIO23 event did not occur
1h = DIO23 event occurred
22DIO22R0hDIO22 event
0h = DIO22 event did not occur
1h = DIO22 event occurred
21DIO21R0hDIO21 event
0h = DIO21 event did not occur
1h = DIO21 event occurred
20DIO20R0hDIO20 event
0h = DIO20 event did not occur
1h = DIO20 event occurred
19DIO19R0hDIO19 event
0h = DIO19 event did not occur
1h = DIO19 event occurred
18DIO18R0hDIO18 event
0h = DIO18 event did not occur
1h = DIO18 event occurred
17DIO17R0hDIO17 event
0h = DIO17 event did not occur
1h = DIO17 event occurred
16DIO16R0hDIO16 event
0h = DIO16 event did not occur
1h = DIO16 event occurred
15-0RESERVEDR0h

9.3.26 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 9-29 and described in Table 9-29.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 9-29 ISET
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
RESERVED
W-0h
76543210
RESERVED
W-0h
Table 9-29 ISET Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hDIO31 event
0h = No effect
1h = Sets DIO31 in RIS register
30DIO30W0hDIO30 event
0h = No effect
1h = Sets DIO30 in RIS register
29DIO29W0hDIO29 event
0h = No effect
1h = Sets DIO29 in RIS register
28DIO28W0hDIO28 event
0h = No effect
1h = Sets DIO28 in RIS register
27DIO27W0hDIO27 event
0h = No effect
1h = Sets DIO27 in RIS register
26DIO26W0hDIO26 event
0h = No effect
1h = Sets DIO26 in RIS register
25DIO25W0hDIO25 event
0h = No effect
1h = Sets DIO25 in RIS register
24DIO24W0hDIO24 event
0h = No effect
1h = Sets DIO24 in RIS register
23DIO23W0hDIO23 event
0h = No effect
1h = Sets DIO23 in RIS register
22DIO22W0hDIO22 event
0h = No effect
1h = Sets DIO22 in RIS register
21DIO21W0hDIO21 event
0h = No effect
1h = Sets DIO21 in RIS register
20DIO20W0hDIO20 event
0h = No effect
1h = Sets DIO20 in RIS register
19DIO19W0hDIO19 event
0h = No effect
1h = Sets DIO19 in RIS register
18DIO18W0hDIO18 event
0h = No effect
1h = Sets DIO18 in RIS register
17DIO17W0hDIO17 event
0h = No effect
1h = Sets DIO17 in RIS register
16DIO16W0hDIO16 event
0h = No effect
1h = Sets DIO16 in RIS register
15-0RESERVEDW0h

9.3.27 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 9-30 and described in Table 9-30.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 9-30 ICLR
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
RESERVED
W-0h
76543210
RESERVED
W-0h
Table 9-30 ICLR Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hDIO31 event
0h = No effect
1h = Clears DIO31 in RIS register
30DIO30W0hDIO30 event
0h = No effect
1h = Clears DIO30 in RIS register
29DIO29W0hDIO29 event
0h = No effect
1h = Clears DIO29 in RIS register
28DIO28W0hDIO28 event
0h = No effect
1h = Clears DIO28 in RIS register
27DIO27W0hDIO27 event
0h = No effect
1h = Clears DIO27 in RIS register
26DIO26W0hDIO26 event
0h = No effect
1h = Clears DIO26 in RIS register
25DIO25W0hDIO25 event
0h = No effect
1h = Clears DIO25 in RIS register
24DIO24W0hDIO24 event
0h = No effect
1h = Clears DIO24 in RIS register
23DIO23W0hDIO23 event
0h = No effect
1h = Clears DIO23 in RIS register
22DIO22W0hDIO22 event
0h = No effect
1h = Clears DIO22 in RIS register
21DIO21W0hDIO21 event
0h = No effect
1h = Clears DIO21 in RIS register
20DIO20W0hDIO20 event
0h = No effect
1h = Clears DIO20 in RIS register
19DIO19W0hDIO19 event
0h = No effect
1h = Clears DIO19 in RIS register
18DIO18W0hDIO18 event
0h = No effect
1h = Clears DIO18 in RIS register
17DIO17W0hDIO17 event
0h = No effect
1h = Clears DIO17 in RIS register
16DIO16W0hDIO16 event
0h = No effect
1h = Clears DIO16 in RIS register
15-0RESERVEDW0h

9.3.28 EVT_MODE (Offset = 10E0h) [Reset = 00000029h]

EVT_MODE is shown in Figure 9-31 and described in Table 9-31.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 9-31 EVT_MODE
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDEVT2_CFGEVT1_CFGINT0_CFG
R/W-R-2hR-2hR-1h
Table 9-31 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4EVT2_CFGR2hEvent line mode select for event corresponding to none.GEN_EVENT1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR2hEvent line mode select for event corresponding to none.GEN_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to none.CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

9.3.29 DESC (Offset = 10FCh) [Reset = 16110000h]

DESC is shown in Figure 9-32 and described in Table 9-32.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 9-32 DESC
31302928272625242322212019181716
MODULEID
R-1611h
1514131211109876543210
FEATUREVERRESERVEDMAJREVMINREV
R-R-R-R-
Table 9-32 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR1611hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
0h = Smallest value
Fh = Highest possible value
11-8RESERVEDR0h
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

9.3.30 DOUT3_0 (Offset = 1200h) [Reset = 00000000h]

DOUT3_0 is shown in Figure 9-33 and described in Table 9-33.

Return to the Summary Table.

Data output for pins configured as DIO3 to DIO0. This is an alias register for byte access to bits 3 to 0 in DOUT31_0 register.

Figure 9-33 DOUT3_0
3130292827262524
RESERVEDDIO3
W-0hW-0h
2322212019181716
RESERVEDDIO2
W-0hW-0h
15141312111098
RESERVEDDIO1
W-0hW-0h
76543210
RESERVEDDIO0
W-0hW-0h
Table 9-33 DOUT3_0 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO3W0hThis bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO2W0hThis bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO1W0hThis bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO0W0hThis bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.31 DOUT7_4 (Offset = 1204h) [Reset = 00000000h]

DOUT7_4 is shown in Figure 9-34 and described in Table 9-34.

Return to the Summary Table.

Data output for pins configured as DIO7 to DIO4. This is an alias register for byte access to bits 7 to 4 in DOUT31_0 register.

Figure 9-34 DOUT7_4
3130292827262524
RESERVEDDIO7
W-0hW-0h
2322212019181716
RESERVEDDIO6
W-0hW-0h
15141312111098
RESERVEDDIO5
W-0hW-0h
76543210
RESERVEDDIO4
W-0hW-0h
Table 9-34 DOUT7_4 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO7W0hThis bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO6W0hThis bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO5W0hThis bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO4W0hThis bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.32 DOUT11_8 (Offset = 1208h) [Reset = 00000000h]

DOUT11_8 is shown in Figure 9-35 and described in Table 9-35.

Return to the Summary Table.

Data output for pins configured as DIO11 to DIO8. This is an alias register for byte access to bits 11 to 8 in DOUT31_0 register.

Figure 9-35 DOUT11_8
3130292827262524
RESERVEDDIO11
W-0hW-0h
2322212019181716
RESERVEDDIO10
W-0hW-0h
15141312111098
RESERVEDDIO9
W-0hW-0h
76543210
RESERVEDDIO8
W-0hW-0h
Table 9-35 DOUT11_8 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO11W0hThis bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO10W0hThis bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO9W0hThis bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO8W0hThis bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.33 DOUT15_12 (Offset = 120Ch) [Reset = 00000000h]

DOUT15_12 is shown in Figure 9-36 and described in Table 9-36.

Return to the Summary Table.

Data output for pins configured as DIO15 to DIO12. This is an alias register for byte access to bits 15 to 12 in DOUT31_0 register.

Figure 9-36 DOUT15_12
3130292827262524
RESERVEDDIO15
W-0hW-0h
2322212019181716
RESERVEDDIO14
W-0hW-0h
15141312111098
RESERVEDDIO13
W-0hW-0h
76543210
RESERVEDDIO12
W-0hW-0h
Table 9-36 DOUT15_12 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO15W0hThis bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO14W0hThis bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO13W0hThis bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO12W0hThis bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.34 DOUT19_16 (Offset = 1210h) [Reset = 00000000h]

DOUT19_16 is shown in Figure 9-37 and described in Table 9-37.

Return to the Summary Table.

Data output for pins configured as DIO19 to DIO16. This is an alias register for byte access to bits 19 to 16 in DOUT31_0 register.

Figure 9-37 DOUT19_16
3130292827262524
RESERVEDDIO19
W-0hW-0h
2322212019181716
RESERVEDDIO18
W-0hW-0h
15141312111098
RESERVEDDIO17
W-0hW-0h
76543210
RESERVEDDIO16
W-0hW-0h
Table 9-37 DOUT19_16 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO19W0hThis bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO18W0hThis bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO17W0hThis bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO16W0hThis bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.35 DOUT23_20 (Offset = 1214h) [Reset = 00000000h]

DOUT23_20 is shown in Figure 9-38 and described in Table 9-38.

Return to the Summary Table.

Data output for pins configured as DIO23 to DIO20. This is an alias register for byte access to bits 23 to 20 in DOUT31_0 register.

Figure 9-38 DOUT23_20
3130292827262524
RESERVEDDIO23
W-0hW-0h
2322212019181716
RESERVEDDIO22
W-0hW-0h
15141312111098
RESERVEDDIO21
W-0hW-0h
76543210
RESERVEDDIO20
W-0hW-0h
Table 9-38 DOUT23_20 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO23W0hThis bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO22W0hThis bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO21W0hThis bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO20W0hThis bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.36 DOUT27_24 (Offset = 1218h) [Reset = 00000000h]

DOUT27_24 is shown in Figure 9-39 and described in Table 9-39.

Return to the Summary Table.

Data output for pins configured as DIO27 to DIO24. This is an alias register for byte access to bits 27 to 24 in DOUT31_0 register.

Figure 9-39 DOUT27_24
3130292827262524
RESERVEDDIO27
W-0hW-0h
2322212019181716
RESERVEDDIO26
W-0hW-0h
15141312111098
RESERVEDDIO25
W-0hW-0h
76543210
RESERVEDDIO24
W-0hW-0h
Table 9-39 DOUT27_24 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO27W0hThis bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO26W0hThis bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO25W0hThis bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO24W0hThis bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.37 DOUT31_28 (Offset = 121Ch) [Reset = 00000000h]

DOUT31_28 is shown in Figure 9-40 and described in Table 9-40.

Return to the Summary Table.

Data output for pins configured as DIO31 to DIO28. This is an alias register for byte access to bits 31 to 28 in DOUT31_0 register.

Figure 9-40 DOUT31_28
3130292827262524
RESERVEDDIO31
W-0hW-0h
2322212019181716
RESERVEDDIO30
W-0hW-0h
15141312111098
RESERVEDDIO29
W-0hW-0h
76543210
RESERVEDDIO28
W-0hW-0h
Table 9-40 DOUT31_28 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDW0h
24DIO31W0hThis bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDW0h
16DIO30W0hThis bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDW0h
8DIO29W0hThis bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDW0h
0DIO28W0hThis bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.38 DOUT31_0 (Offset = 1280h) [Reset = 00000000h]

DOUT31_0 is shown in Figure 9-41 and described in Table 9-41.

Return to the Summary Table.

Data output for pins configured as DIO31 to DIO0.

Figure 9-41 DOUT31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-41 DOUT31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31R/W0hThis bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
30DIO30R/W0hThis bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
29DIO29R/W0hThis bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
28DIO28R/W0hThis bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
27DIO27R/W0hThis bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
26DIO26R/W0hThis bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
25DIO25R/W0hThis bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
24DIO24R/W0hThis bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
23DIO23R/W0hThis bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
22DIO22R/W0hThis bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
21DIO21R/W0hThis bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
20DIO20R/W0hThis bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
19DIO19R/W0hThis bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
18DIO18R/W0hThis bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
17DIO17R/W0hThis bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
16DIO16R/W0hThis bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
15DIO15R/W0hThis bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
14DIO14R/W0hThis bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
13DIO13R/W0hThis bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
12DIO12R/W0hThis bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
11DIO11R/W0hThis bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
10DIO10R/W0hThis bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
9DIO9R/W0hThis bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
8DIO8R/W0hThis bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
7DIO7R/W0hThis bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
6DIO6R/W0hThis bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
5DIO5R/W0hThis bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
4DIO4R/W0hThis bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
3DIO3R/W0hThis bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
2DIO2R/W0hThis bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
1DIO1R/W0hThis bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1
0DIO0R/W0hThis bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.
0h = Output is set to 0
1h = Output is set to 1

9.3.39 DOUTSET31_0 (Offset = 1290h) [Reset = 00000000h]

DOUTSET31_0 is shown in Figure 9-42 and described in Table 9-42.

Return to the Summary Table.

Writing 1 to a bit position in this register sets the corresponding bit in the DOUT31_0 register.

Figure 9-42 DOUTSET31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-42 DOUTSET31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hWriting 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO31 in DOUT31_0
30DIO30W0hWriting 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO30 in DOUT31_0
29DIO29W0hWriting 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO29 in DOUT31_0
28DIO28W0hWriting 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO28 in DOUT31_0
27DIO27W0hWriting 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO27 in DOUT31_0
26DIO26W0hWriting 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO26 in DOUT31_0
25DIO25W0hWriting 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO25 in DOUT31_0
24DIO24W0hWriting 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO24 in DOUT31_0
23DIO23W0hWriting 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO23 in DOUT31_0
22DIO22W0hWriting 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO22 in DOUT31_0
21DIO21W0hWriting 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO21 in DOUT31_0
20DIO20W0hWriting 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO20 in DOUT31_0
19DIO19W0hWriting 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO19 in DOUT31_0
18DIO18W0hWriting 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO18 in DOUT31_0
17DIO17W0hWriting 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO17 in DOUT31_0
16DIO16W0hWriting 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO16 in DOUT31_0
15DIO15W0hWriting 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO15 in DOUT31_0
14DIO14W0hWriting 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO14 in DOUT31_0
13DIO13W0hWriting 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO13 in DOUT31_0
12DIO12W0hWriting 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO12 in DOUT31_0
11DIO11W0hWriting 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO11 in DOUT31_0
10DIO10W0hWriting 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO10 in DOUT31_0
9DIO9W0hWriting 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO9 in DOUT31_0
8DIO8W0hWriting 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO8 in DOUT31_0
7DIO7W0hWriting 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO7 in DOUT31_0
6DIO6W0hWriting 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO6 in DOUT31_0
5DIO5W0hWriting 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO5 in DOUT31_0
4DIO4W0hWriting 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO4 in DOUT31_0
3DIO3W0hWriting 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO3 in DOUT31_0
2DIO2W0hWriting 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO2 in DOUT31_0
1DIO1W0hWriting 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO1 in DOUT31_0
0DIO0W0hWriting 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO0 in DOUT31_0

9.3.40 DOUTCLR31_0 (Offset = 12A0h) [Reset = 00000000h]

DOUTCLR31_0 is shown in Figure 9-43 and described in Table 9-43.

Return to the Summary Table.

Writing 1 to a bit position in this register clears the corresponding bit in the DOUT31_0 register.

Figure 9-43 DOUTCLR31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-43 DOUTCLR31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hWriting 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO31 in DOUT31_0
30DIO30W0hWriting 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO30 in DOUT31_0
29DIO29W0hWriting 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO29 in DOUT31_0
28DIO28W0hWriting 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO28 in DOUT31_0
27DIO27W0hWriting 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO27 in DOUT31_0
26DIO26W0hWriting 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO26 in DOUT31_0
25DIO25W0hWriting 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO25 in DOUT31_0
24DIO24W0hWriting 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO24 in DOUT31_0
23DIO23W0hWriting 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO23 in DOUT31_0
22DIO22W0hWriting 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO22 in DOUT31_0
21DIO21W0hWriting 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO21 in DOUT31_0
20DIO20W0hWriting 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO20 in DOUT31_0
19DIO19W0hWriting 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO19 in DOUT31_0
18DIO18W0hWriting 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO18 in DOUT31_0
17DIO17W0hWriting 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO17 in DOUT31_0
16DIO16W0hWriting 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO16 in DOUT31_0
15DIO15W0hWriting 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO15 in DOUT31_0
14DIO14W0hWriting 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO14 in DOUT31_0
13DIO13W0hWriting 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO13 in DOUT31_0
12DIO12W0hWriting 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO12 in DOUT31_0
11DIO11W0hWriting 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO11 in DOUT31_0
10DIO10W0hWriting 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO10 in DOUT31_0
9DIO9W0hWriting 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO9 in DOUT31_0
8DIO8W0hWriting 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO8 in DOUT31_0
7DIO7W0hWriting 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO7 in DOUT31_0
6DIO6W0hWriting 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO6 in DOUT31_0
5DIO5W0hWriting 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO5 in DOUT31_0
4DIO4W0hWriting 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO4 in DOUT31_0
3DIO3W0hWriting 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO3 in DOUT31_0
2DIO2W0hWriting 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO2 in DOUT31_0
1DIO1W0hWriting 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO1 in DOUT31_0
0DIO0W0hWriting 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO0 in DOUT31_0

9.3.41 DOUTTGL31_0 (Offset = 12B0h) [Reset = 00000000h]

DOUTTGL31_0 is shown in Figure 9-44 and described in Table 9-44.

Return to the Summary Table.

Writing 1 to a bit position in this register will invert the corresponding DIO output.

Figure 9-44 DOUTTGL31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-44 DOUTTGL31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hThis bit is used to toggle DIO31 output.
0h = No effect
1h = Toggle output
30DIO30W0hThis bit is used to toggle DIO30 output.
0h = No effect
1h = Toggle output
29DIO29W0hThis bit is used to toggle DIO29 output.
0h = No effect
1h = Toggle output
28DIO28W0hThis bit is used to toggle DIO28 output.
0h = No effect
1h = Toggle output
27DIO27W0hThis bit is used to toggle DIO27 output.
0h = No effect
1h = Toggle output
26DIO26W0hThis bit is used to toggle DIO26 output.
0h = No effect
1h = Toggle output
25DIO25W0hThis bit is used to toggle DIO25 output.
0h = No effect
1h = Toggle output
24DIO24W0hThis bit is used to toggle DIO24 output.
0h = No effect
1h = Toggle output
23DIO23W0hThis bit is used to toggle DIO23 output.
0h = No effect
1h = Toggle output
22DIO22W0hThis bit is used to toggle DIO22 output.
0h = No effect
1h = Toggle output
21DIO21W0hThis bit is used to toggle DIO21 output.
0h = No effect
1h = Toggle output
20DIO20W0hThis bit is used to toggle DIO20 output.
0h = No effect
1h = Toggle output
19DIO19W0hThis bit is used to toggle DIO19 output.
0h = No effect
1h = Toggle output
18DIO18W0hThis bit is used to toggle DIO18 output.
0h = No effect
1h = Toggle output
17DIO17W0hThis bit is used to toggle DIO17 output.
0h = No effect
1h = Toggle output
16DIO16W0hThis bit is used to toggle DIO16 output.
0h = No effect
1h = Toggle output
15DIO15W0hThis bit is used to toggle DIO15 output.
0h = No effect
1h = Toggle output
14DIO14W0hThis bit is used to toggle DIO14 output.
0h = No effect
1h = Toggle output
13DIO13W0hThis bit is used to toggle DIO13 output.
0h = No effect
1h = Toggle output
12DIO12W0hThis bit is used to toggle DIO12 output.
0h = No effect
1h = Toggle output
11DIO11W0hThis bit is used to toggle DIO11 output.
0h = No effect
1h = Toggle output
10DIO10W0hThis bit is used to toggle DIO10 output.
0h = No effect
1h = Toggle output
9DIO9W0hThis bit is used to toggle DIO9 output.
0h = No effect
1h = Toggle output
8DIO8W0hThis bit is used to toggle DIO8 output.
0h = No effect
1h = Toggle output
7DIO7W0hThis bit is used to toggle DIO7 output.
0h = No effect
1h = Toggle output
6DIO6W0hThis bit is used to toggle DIO6 output.
0h = No effect
1h = Toggle output
5DIO5W0hThis bit is used to toggle DIO5 output.
0h = No effect
1h = Toggle output
4DIO4W0hThis bit is used to toggle DIO4 output.
0h = No effect
1h = Toggle output
3DIO3W0hThis bit is used to toggle DIO3 output.
0h = No effect
1h = Toggle output
2DIO2W0hThis bit is used to toggle DIO2 output.
0h = No effect
1h = Toggle output
1DIO1W0hThis bit is used to toggle DIO1 output.
0h = No effect
1h = Toggle output
0DIO0W0hThis bit is used to toggle DIO0 output.
0h = No effect
1h = Toggle output

9.3.42 DOE31_0 (Offset = 12C0h) [Reset = 00000000h]

DOE31_0 is shown in Figure 9-45 and described in Table 9-45.

Return to the Summary Table.

This register is used to enable the data outputs for DIO31 to DIO0.

Figure 9-45 DOE31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-45 DOE31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31R/W0hEnables data output for DIO31.
0h = Output disabled
1h = Output enabled
30DIO30R/W0hEnables data output for DIO30.
0h = Output disabled
1h = Output enabled
29DIO29R/W0hEnables data output for DIO29.
0h = Output disabled
1h = Output enabled
28DIO28R/W0hEnables data output for DIO28.
0h = Output disabled
1h = Output enabled
27DIO27R/W0hEnables data output for DIO27.
0h = Output disabled
1h = Output enabled
26DIO26R/W0hEnables data output for DIO26.
0h = Output disabled
1h = Output enabled
25DIO25R/W0hEnables data output for DIO25.
0h = Output disabled
1h = Output enabled
24DIO24R/W0hEnables data output for DIO24.
0h = Output disabled
1h = Output enabled
23DIO23R/W0hEnables data output for DIO23.
0h = Output disabled
1h = Output enabled
22DIO22R/W0hEnables data output for DIO22.
0h = Output disabled
1h = Output enabled
21DIO21R/W0hEnables data output for DIO21.
0h = Output disabled
1h = Output enabled
20DIO20R/W0hEnables data output for DIO20.
0h = Output disabled
1h = Output enabled
19DIO19R/W0hEnables data output for DIO19.
0h = Output disabled
1h = Output enabled
18DIO18R/W0hEnables data output for DIO18.
0h = Output disabled
1h = Output enabled
17DIO17R/W0hEnables data output for DIO17.
0h = Output disabled
1h = Output enabled
16DIO16R/W0hEnables data output for DIO16.
0h = Output disabled
1h = Output enabled
15DIO15R/W0hEnables data output for DIO15.
0h = Output disabled
1h = Output enabled
14DIO14R/W0hEnables data output for DIO14.
0h = Output disabled
1h = Output enabled
13DIO13R/W0hEnables data output for DIO13.
0h = Output disabled
1h = Output enabled
12DIO12R/W0hEnables data output for DIO12.
0h = Output disabled
1h = Output enabled
11DIO11R/W0hEnables data output for DIO11.
0h = Output disabled
1h = Output enabled
10DIO10R/W0hEnables data output for DIO10.
0h = Output disabled
1h = Output enabled
9DIO9R/W0hEnables data output for DIO9.
0h = Output disabled
1h = Output enabled
8DIO8R/W0hEnables data output for DIO8.
0h = Output disabled
1h = Output enabled
7DIO7R/W0hEnables data output for DIO7.
0h = Output disabled
1h = Output enabled
6DIO6R/W0hEnables data output for DIO6.
0h = Output disabled
1h = Output enabled
5DIO5R/W0hEnables data output for DIO5.
0h = Output disabled
1h = Output enabled
4DIO4R/W0hEnables data output for DIO4.
0h = Output disabled
1h = Output enabled
3DIO3R/W0hEnables data output for DIO3.
0h = Output disabled
1h = Output enabled
2DIO2R/W0hEnables data output for DIO2.
0h = Output disabled
1h = Output enabled
1DIO1R/W0hEnables data output for DIO1.
0h = Output disabled
1h = Output enabled
0DIO0R/W0hEnables data output for DIO0.
0h = Output disabled
1h = Output enabled

9.3.43 DOESET31_0 (Offset = 12D0h) [Reset = 00000000h]

DOESET31_0 is shown in Figure 9-46 and described in Table 9-46.

Return to the Summary Table.

Writing 1 to a bit position in this register sets the corresponding bit in the DOE31_0 register.

Figure 9-46 DOESET31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-46 DOESET31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hWriting 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO31 in DOE31_0
30DIO30W0hWriting 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO30 in DOE31_0
29DIO29W0hWriting 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO29 in DOE31_0
28DIO28W0hWriting 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO28 in DOE31_0
27DIO27W0hWriting 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO27 in DOE31_0
26DIO26W0hWriting 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO26 in DOE31_0
25DIO25W0hWriting 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO25 in DOE31_0
24DIO24W0hWriting 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO24 in DOE31_0
23DIO23W0hWriting 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO23 in DOE31_0
22DIO22W0hWriting 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO22 in DOE31_0
21DIO21W0hWriting 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO21 in DOE31_0
20DIO20W0hWriting 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO20 in DOE31_0
19DIO19W0hWriting 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO19 in DOE31_0
18DIO18W0hWriting 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO18 in DOE31_0
17DIO17W0hWriting 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO17 in DOE31_0
16DIO16W0hWriting 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO16 in DOE31_0
15DIO15W0hWriting 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO15 in DOE31_0
14DIO14W0hWriting 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO14 in DOE31_0
13DIO13W0hWriting 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO13 in DOE31_0
12DIO12W0hWriting 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO12 in DOE31_0
11DIO11W0hWriting 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO11 in DOE31_0
10DIO10W0hWriting 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO10 in DOE31_0
9DIO9W0hWriting 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO9 in DOE31_0
8DIO8W0hWriting 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO8 in DOE31_0
7DIO7W0hWriting 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO7 in DOE31_0
6DIO6W0hWriting 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO6 in DOE31_0
5DIO5W0hWriting 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO5 in DOE31_0
4DIO4W0hWriting 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO4 in DOE31_0
3DIO3W0hWriting 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO3 in DOE31_0
2DIO2W0hWriting 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO2 in DOE31_0
1DIO1W0hWriting 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO1 in DOE31_0
0DIO0W0hWriting 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Sets DIO0 in DOE31_0

9.3.44 DOECLR31_0 (Offset = 12E0h) [Reset = 00000000h]

DOECLR31_0 is shown in Figure 9-47 and described in Table 9-47.

Return to the Summary Table.

Writing 1 to a bit position in this register clears the corresponding bit in the DOE31_0 register.

Figure 9-47 DOECLR31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 9-47 DOECLR31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31W0hWriting 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO31 in DOE31_0
30DIO30W0hWriting 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO30 in DOE31_0
29DIO29W0hWriting 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO29 in DOE31_0
28DIO28W0hWriting 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO28 in DOE31_0
27DIO27W0hWriting 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO27 in DOE31_0
26DIO26W0hWriting 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO26 in DOE31_0
25DIO25W0hWriting 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO25 in DOE31_0
24DIO24W0hWriting 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO24 in DOE31_0
23DIO23W0hWriting 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO23 in DOE31_0
22DIO22W0hWriting 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO22 in DOE31_0
21DIO21W0hWriting 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO21 in DOE31_0
20DIO20W0hWriting 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO20 in DOE31_0
19DIO19W0hWriting 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO19 in DOE31_0
18DIO18W0hWriting 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO18 in DOE31_0
17DIO17W0hWriting 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO17 in DOE31_0
16DIO16W0hWriting 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO16 in DOE31_0
15DIO15W0hWriting 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO15 in DOE31_0
14DIO14W0hWriting 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO14 in DOE31_0
13DIO13W0hWriting 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO13 in DOE31_0
12DIO12W0hWriting 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO12 in DOE31_0
11DIO11W0hWriting 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO11 in DOE31_0
10DIO10W0hWriting 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO10 in DOE31_0
9DIO9W0hWriting 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO9 in DOE31_0
8DIO8W0hWriting 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO8 in DOE31_0
7DIO7W0hWriting 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO7 in DOE31_0
6DIO6W0hWriting 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO6 in DOE31_0
5DIO5W0hWriting 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO5 in DOE31_0
4DIO4W0hWriting 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO4 in DOE31_0
3DIO3W0hWriting 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO3 in DOE31_0
2DIO2W0hWriting 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO2 in DOE31_0
1DIO1W0hWriting 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO1 in DOE31_0
0DIO0W0hWriting 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.
0h = No effect
1h = Clears DIO0 in DOE31_0

9.3.45 DIN3_0 (Offset = 1300h) [Reset = 00000000h]

DIN3_0 is shown in Figure 9-48 and described in Table 9-48.

Return to the Summary Table.

Data input from pins configured as DIO3 to DIO0. This is an alias register for byte access to bits 3 to 0 in DIN31_0 register.

Figure 9-48 DIN3_0
3130292827262524
RESERVEDDIO3
R-0hR-0h
2322212019181716
RESERVEDDIO2
R-0hR-0h
15141312111098
RESERVEDDIO1
R-0hR-0h
76543210
RESERVEDDIO0
R-0hR-0h
Table 9-48 DIN3_0 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO3R0hThis bit reads the data input value of DIO3.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO2R0hThis bit reads the data input value of DIO2.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO1R0hThis bit reads the data input value of DIO1.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO0R0hThis bit reads the data input value of DIO0.
0h = Input value is 0
1h = Input value is 1

9.3.46 DIN7_4 (Offset = 1304h) [Reset = 00000000h]

DIN7_4 is shown in Figure 9-49 and described in Table 9-49.

Return to the Summary Table.

Data input from pins configured as DIO7 to DIO4. This is an alias register for byte access to bits 7 to 4 in DIN31_0 register.

Figure 9-49 DIN7_4
3130292827262524
RESERVEDDIO7
R-0hR-0h
2322212019181716
RESERVEDDIO6
R-0hR-0h
15141312111098
RESERVEDDIO5
R-0hR-0h
76543210
RESERVEDDIO4
R-0hR-0h
Table 9-49 DIN7_4 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO7R0hThis bit reads the data input value of DIO7.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO6R0hThis bit reads the data input value of DIO6.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO5R0hThis bit reads the data input value of DIO5.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO4R0hThis bit reads the data input value of DIO4.
0h = Input value is 0
1h = Input value is 1

9.3.47 DIN11_8 (Offset = 1308h) [Reset = 00000000h]

DIN11_8 is shown in Figure 9-50 and described in Table 9-50.

Return to the Summary Table.

Data input from pins configured as DIO11 to DIO8. This is an alias register for byte access to bits 11 to 8 in DIN31_0 register.

Figure 9-50 DIN11_8
3130292827262524
RESERVEDDIO11
R-0hR-0h
2322212019181716
RESERVEDDIO10
R-0hR-0h
15141312111098
RESERVEDDIO9
R-0hR-0h
76543210
RESERVEDDIO8
R-0hR-0h
Table 9-50 DIN11_8 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO11R0hThis bit reads the data input value of DIO11.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO10R0hThis bit reads the data input value of DIO10.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO9R0hThis bit reads the data input value of DIO9.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO8R0hThis bit reads the data input value of DIO8.
0h = Input value is 0
1h = Input value is 1

9.3.48 DIN15_12 (Offset = 130Ch) [Reset = 00000000h]

DIN15_12 is shown in Figure 9-51 and described in Table 9-51.

Return to the Summary Table.

Data input from pins configured as DIO15 to DIO12. This is an alias register for byte access to bits 15 to 12 in DIN31_0 register.

Figure 9-51 DIN15_12
3130292827262524
RESERVEDDIO15
R-0hR-0h
2322212019181716
RESERVEDDIO14
R-0hR-0h
15141312111098
RESERVEDDIO13
R-0hR-0h
76543210
RESERVEDDIO12
R-0hR-0h
Table 9-51 DIN15_12 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO15R0hThis bit reads the data input value of DIO15.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO14R0hThis bit reads the data input value of DIO14.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO13R0hThis bit reads the data input value of DIO13.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO12R0hThis bit reads the data input value of DIO12.
0h = Input value is 0
1h = Input value is 1

9.3.49 DIN19_16 (Offset = 1310h) [Reset = 00000000h]

DIN19_16 is shown in Figure 9-52 and described in Table 9-52.

Return to the Summary Table.

Data input from pins configured as DIO19 to DIO16. This is an alias register for byte access to bits 19 to 16 in DIN31_0 register.

Figure 9-52 DIN19_16
3130292827262524
RESERVEDDIO19
R-0hR-0h
2322212019181716
RESERVEDDIO18
R-0hR-0h
15141312111098
RESERVEDDIO17
R-0hR-0h
76543210
RESERVEDDIO16
R-0hR-0h
Table 9-52 DIN19_16 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO19R0hThis bit reads the data input value of DIO19.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO18R0hThis bit reads the data input value of DIO18.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO17R0hThis bit reads the data input value of DIO17.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO16R0hThis bit reads the data input value of DIO16.
0h = Input value is 0
1h = Input value is 1

9.3.50 DIN23_20 (Offset = 1314h) [Reset = 00000000h]

DIN23_20 is shown in Figure 9-53 and described in Table 9-53.

Return to the Summary Table.

Data input from pins configured as DIO23 to DIO20. This is an alias register for byte access to bits 23 to 20 in DIN31_0 register.

Figure 9-53 DIN23_20
3130292827262524
RESERVEDDIO23
R-0hR-0h
2322212019181716
RESERVEDDIO22
R-0hR-0h
15141312111098
RESERVEDDIO21
R-0hR-0h
76543210
RESERVEDDIO20
R-0hR-0h
Table 9-53 DIN23_20 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO23R0hThis bit reads the data input value of DIO23.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO22R0hThis bit reads the data input value of DIO22.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO21R0hThis bit reads the data input value of DIO21.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO20R0hThis bit reads the data input value of DIO20.
0h = Input value is 0
1h = Input value is 1

9.3.51 DIN27_24 (Offset = 1318h) [Reset = 00000000h]

DIN27_24 is shown in Figure 9-54 and described in Table 9-54.

Return to the Summary Table.

Data input from pins configured as DIO27 to DIO24. This is an alias register for byte access to bits 27 to 24 in DIN31_0 register.

Figure 9-54 DIN27_24
3130292827262524
RESERVEDDIO27
R-0hR-0h
2322212019181716
RESERVEDDIO26
R-0hR-0h
15141312111098
RESERVEDDIO25
R-0hR-0h
76543210
RESERVEDDIO24
R-0hR-0h
Table 9-54 DIN27_24 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO27R0hThis bit reads the data input value of DIO27.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO26R0hThis bit reads the data input value of DIO26.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO25R0hThis bit reads the data input value of DIO25.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO24R0hThis bit reads the data input value of DIO24.
0h = Input value is 0
1h = Input value is 1

9.3.52 DIN31_28 (Offset = 131Ch) [Reset = 00000000h]

DIN31_28 is shown in Figure 9-55 and described in Table 9-55.

Return to the Summary Table.

Data input from pins configured as DIO31 to DIO28. This is an alias register for byte access to bits 31 to 28 in DIN31_0 register.

Figure 9-55 DIN31_28
3130292827262524
RESERVEDDIO31
R-0hR-0h
2322212019181716
RESERVEDDIO30
R-0hR-0h
15141312111098
RESERVEDDIO29
R-0hR-0h
76543210
RESERVEDDIO28
R-0hR-0h
Table 9-55 DIN31_28 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24DIO31R0hThis bit reads the data input value of DIO31.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16DIO30R0hThis bit reads the data input value of DIO30.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8DIO29R0hThis bit reads the data input value of DIO29.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0DIO28R0hThis bit reads the data input value of DIO28.
0h = Input value is 0
1h = Input value is 1

9.3.53 DIN31_0 (Offset = 1380h) [Reset = 00000000h]

DIN31_0 is shown in Figure 9-56 and described in Table 9-56.

Return to the Summary Table.

Data input value for pins configured as DIO31 to DIO0.

Figure 9-56 DIN31_0
3130292827262524
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 9-56 DIN31_0 Field Descriptions
BitFieldTypeResetDescription
31DIO31R0hThis bit reads the data input value of DIO31.
0h = Input value is 0
1h = Input value is 1
30DIO30R0hThis bit reads the data input value of DIO30.
0h = Input value is 0
1h = Input value is 1
29DIO29R0hThis bit reads the data input value of DIO29.
0h = Input value is 0
1h = Input value is 1
28DIO28R0hThis bit reads the data input value of DIO28.
0h = Input value is 0
1h = Input value is 1
27DIO27R0hThis bit reads the data input value of DIO27.
0h = Input value is 0
1h = Input value is 1
26DIO26R0hThis bit reads the data input value of DIO26.
0h = Input value is 0
1h = Input value is 1
25DIO25R0hThis bit reads the data input value of DIO25.
0h = Input value is 0
1h = Input value is 1
24DIO24R0hThis bit reads the data input value of DIO24.
0h = Input value is 0
1h = Input value is 1
23DIO23R0hThis bit reads the data input value of DIO23.
0h = Input value is 0
1h = Input value is 1
22DIO22R0hThis bit reads the data input value of DIO22.
0h = Input value is 0
1h = Input value is 1
21DIO21R0hThis bit reads the data input value of DIO21.
0h = Input value is 0
1h = Input value is 1
20DIO20R0hThis bit reads the data input value of DIO20.
0h = Input value is 0
1h = Input value is 1
19DIO19R0hThis bit reads the data input value of DIO19.
0h = Input value is 0
1h = Input value is 1
18DIO18R0hThis bit reads the data input value of DIO18.
0h = Input value is 0
1h = Input value is 1
17DIO17R0hThis bit reads the data input value of DIO17.
0h = Input value is 0
1h = Input value is 1
16DIO16R0hThis bit reads the data input value of DIO16.
0h = Input value is 0
1h = Input value is 1
15DIO15R0hThis bit reads the data input value of DIO15.
0h = Input value is 0
1h = Input value is 1
14DIO14R0hThis bit reads the data input value of DIO14.
0h = Input value is 0
1h = Input value is 1
13DIO13R0hThis bit reads the data input value of DIO13.
0h = Input value is 0
1h = Input value is 1
12DIO12R0hThis bit reads the data input value of DIO12.
0h = Input value is 0
1h = Input value is 1
11DIO11R0hThis bit reads the data input value of DIO11.
0h = Input value is 0
1h = Input value is 1
10DIO10R0hThis bit reads the data input value of DIO10.
0h = Input value is 0
1h = Input value is 1
9DIO9R0hThis bit reads the data input value of DIO9.
0h = Input value is 0
1h = Input value is 1
8DIO8R0hThis bit reads the data input value of DIO8.
0h = Input value is 0
1h = Input value is 1
7DIO7R0hThis bit reads the data input value of DIO7.
0h = Input value is 0
1h = Input value is 1
6DIO6R0hThis bit reads the data input value of DIO6.
0h = Input value is 0
1h = Input value is 1
5DIO5R0hThis bit reads the data input value of DIO5.
0h = Input value is 0
1h = Input value is 1
4DIO4R0hThis bit reads the data input value of DIO4.
0h = Input value is 0
1h = Input value is 1
3DIO3R0hThis bit reads the data input value of DIO3.
0h = Input value is 0
1h = Input value is 1
2DIO2R0hThis bit reads the data input value of DIO2.
0h = Input value is 0
1h = Input value is 1
1DIO1R0hThis bit reads the data input value of DIO1.
0h = Input value is 0
1h = Input value is 1
0DIO0R0hThis bit reads the data input value of DIO0.
0h = Input value is 0
1h = Input value is 1

9.3.54 POLARITY15_0 (Offset = 1390h) [Reset = 00000000h]

POLARITY15_0 is shown in Figure 9-57 and described in Table 9-57.

Return to the Summary Table.

This register is used to enable and configure the polarity for input edge detection on DIO15 to DIO0. The corresponding DIO bits in RIS register will be set when the input event matches the configured polarity.

Figure 9-57 POLARITY15_0
31302928272625242322212019181716
DIO15DIO14DIO13DIO12DIO11DIO10DIO9DIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
DIO7DIO6DIO5DIO4DIO3DIO2DIO1DIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-57 POLARITY15_0 Field Descriptions
BitFieldTypeResetDescription
31-30DIO15R/W0hEnables and configures edge detection polarity for DIO15.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
29-28DIO14R/W0hEnables and configures edge detection polarity for DIO14.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
27-26DIO13R/W0hEnables and configures edge detection polarity for DIO13.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
25-24DIO12R/W0hEnables and configures edge detection polarity for DIO12.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
23-22DIO11R/W0hEnables and configures edge detection polarity for DIO11.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
21-20DIO10R/W0hEnables and configures edge detection polarity for DIO10.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
19-18DIO9R/W0hEnables and configures edge detection polarity for DIO9.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
17-16DIO8R/W0hEnables and configures edge detection polarity for DIO8.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
15-14DIO7R/W0hEnables and configures edge detection polarity for DIO7.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
13-12DIO6R/W0hEnables and configures edge detection polarity for DIO6.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
11-10DIO5R/W0hEnables and configures edge detection polarity for DIO5.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
9-8DIO4R/W0hEnables and configures edge detection polarity for DIO4.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
7-6DIO3R/W0hEnables and configures edge detection polarity for DIO3.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
5-4DIO2R/W0hEnables and configures edge detection polarity for DIO2.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
3-2DIO1R/W0hEnables and configures edge detection polarity for DIO1.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
1-0DIO0R/W0hEnables and configures edge detection polarity for DIO0.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event

9.3.55 POLARITY31_16 (Offset = 13A0h) [Reset = 00000000h]

POLARITY31_16 is shown in Figure 9-58 and described in Table 9-58.

Return to the Summary Table.

This register is used to enable and configure the polarity for input edge detection on DIO31 to DIO16. The corresponding DIO bits in RIS register will be set when the input event matches the configured polarity.

Figure 9-58 POLARITY31_16
31302928272625242322212019181716
DIO31DIO30DIO29DIO28DIO27DIO26DIO25DIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
DIO23DIO22DIO21DIO20DIO19DIO18DIO17DIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-58 POLARITY31_16 Field Descriptions
BitFieldTypeResetDescription
31-30DIO31R/W0hEnables and configures edge detection polarity for DIO31.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
29-28DIO30R/W0hEnables and configures edge detection polarity for DIO30.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
27-26DIO29R/W0hEnables and configures edge detection polarity for DIO29.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
25-24DIO28R/W0hEnables and configures edge detection polarity for DIO28.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
23-22DIO27R/W0hEnables and configures edge detection polarity for DIO27.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
21-20DIO26R/W0hEnables and configures edge detection polarity for DIO26.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
19-18DIO25R/W0hEnables and configures edge detection polarity for DIO25.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
17-16DIO24R/W0hEnables and configures edge detection polarity for DIO24.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
15-14DIO23R/W0hEnables and configures edge detection polarity for DIO23.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
13-12DIO22R/W0hEnables and configures edge detection polarity for DIO22.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
11-10DIO21R/W0hEnables and configures edge detection polarity for DIO21.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
9-8DIO20R/W0hEnables and configures edge detection polarity for DIO20.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
7-6DIO19R/W0hEnables and configures edge detection polarity for DIO19.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
5-4DIO18R/W0hEnables and configures edge detection polarity for DIO18.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
3-2DIO17R/W0hEnables and configures edge detection polarity for DIO17.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
1-0DIO16R/W0hEnables and configures edge detection polarity for DIO16.
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event

9.3.56 CTL (Offset = 1400h) [Reset = 00000000h]

CTL is shown in Figure 9-59 and described in Table 9-59.

Return to the Summary Table.

GPIO Control Register

Figure 9-59 CTL
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDFASTWAKEONLY
R/W-0hR/W-0h
Table 9-59 CTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0FASTWAKEONLYR/W0hFASTWAKEONLY for the global control of fastwake
0h = The global control of fastwake is not enabled, per bit fast wake feature depends on FASTWAKE.DIN
1h = The global control of fastwake is enabled

9.3.57 FASTWAKE (Offset = 1404h) [Reset = 00000000h]

FASTWAKE is shown in Figure 9-60 and described in Table 9-60.

Return to the Summary Table.

This is per bit fast wake enable for the bit slice, allows the GPIO module to stay in a low power state and not require high speed clocking of the input synchronizer or filter

Figure 9-60 FASTWAKE
3130292827262524
DIN31DIN30DIN29DIN28DIN27DIN26DIN25DIN24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DIN23DIN22DIN21DIN20DIN19DIN18DIN17DIN16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DIN15DIN14DIN13DIN12DIN11DIN10DIN9DIN8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DIN7DIN6DIN5DIN4DIN3DIN2DIN1DIN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-60 FASTWAKE Field Descriptions
BitFieldTypeResetDescription
31DIN31R/W0hEnable fastwake feature for DIN31
0h = fastwake feature is disabled
1h = fastwake feature is enabled
30DIN30R/W0hEnable fastwake feature for DIN30
0h = fastwake feature is disabled
1h = fastwake feature is enabled
29DIN29R/W0hEnable fastwake feature for DIN29
0h = fastwake feature is disabled
1h = fastwake feature is enabled
28DIN28R/W0hEnable fastwake feature for DIN29
0h = fastwake feature is disabled
1h = fastwake feature is enabled
27DIN27R/W0hEnable fastwake feature for DIN27
0h = fastwake feature is disabled
1h = fastwake feature is enabled
26DIN26R/W0hEnable fastwake feature for DIN26
0h = fastwake feature is disabled
1h = fastwake feature is enabled
25DIN25R/W0hEnable fastwake feature for DIN25
0h = fastwake feature is disabled
1h = fastwake feature is enabled
24DIN24R/W0hEnable fastwake feature for DIN24
0h = fastwake feature is disabled
1h = fastwake feature is enabled
23DIN23R/W0hEnable fastwake feature for DIN23
0h = fastwake feature is disabled
1h = fastwake feature is enabled
22DIN22R/W0hEnable fastwake feature for DIN22
0h = fastwake feature is disabled
1h = fastwake feature is enabled
21DIN21R/W0hEnable fastwake feature for DIN21
0h = fastwake feature is disabled
1h = fastwake feature is enabled
20DIN20R/W0hEnable fastwake feature for DIN20
0h = fastwake feature is disabled
1h = fastwake feature is enabled
19DIN19R/W0hEnable fastwake feature for DIN19
0h = fastwake feature is disabled
1h = fastwake feature is enabled
18DIN18R/W0hEnable fastwake feature for DIN18
0h = fastwake feature is disabled
1h = fastwake feature is enabled
17DIN17R/W0hEnable fastwake feature for DIN17
0h = fastwake feature is disabled
1h = fastwake feature is enabled
16DIN16R/W0hEnable fastwake feature for DIN16
0h = fastwake feature is disabled
1h = fastwake feature is enabled
15DIN15R/W0hEnable fastwake feature for DIN15
0h = fastwake feature is disabled
1h = fastwake feature is enabled
14DIN14R/W0hEnable fastwake feature for DIN14
0h = fastwake feature is disabled
1h = fastwake feature is enabled
13DIN13R/W0hEnable fastwake feature for DIN13
0h = fastwake feature is disabled
1h = fastwake feature is enabled
12DIN12R/W0hEnable fastwake feature for DIN12
0h = fastwake feature is disabled
1h = fastwake feature is enabled
11DIN11R/W0hEnable fastwake feature for DIN11
0h = fastwake feature is disabled
1h = fastwake feature is enabled
10DIN10R/W0hEnable fastwake feature for DIN10
0h = fastwake feature is disabled
1h = fastwake feature is enabled
9DIN9R/W0hEnable fastwake feature for DIN9
0h = fastwake feature is disabled
1h = fastwake feature is enabled
8DIN8R/W0hEnable fastwake feature for DIN8
0h = fastwake feature is disabled
1h = fastwake feature is enabled
7DIN7R/W0hEnable fastwake feature for DIN7
0h = fastwake feature is disabled
1h = fastwake feature is enabled
6DIN6R/W0hEnable fastwake feature for DIN6
0h = fastwake feature is disabled
1h = fastwake feature is enabled
5DIN5R/W0hEnable fastwake feature for DIN5
0h = fastwake feature is disabled
1h = fastwake feature is enabled
4DIN4R/W0hEnable fastwake feature for DIN4
0h = fastwake feature is disabled
1h = fastwake feature is enabled
3DIN3R/W0hEnable fastwake feature for DIN3
0h = fastwake feature is disabled
1h = fastwake feature is enabled
2DIN2R/W0hEnable fastwake feature for DIN2
0h = fastwake feature is disabled
1h = fastwake feature is enabled
1DIN1R/W0hEnable fastwake feature for DIN1
0h = fastwake feature is disabled
1h = fastwake feature is enabled
0DIN0R/W0hEnable fastwake feature for DIN0
0h = fastwake feature is disabled
1h = fastwake feature is enabled

9.3.58 SUB0CFG (Offset = 1500h) [Reset = 00000000h]

SUB0CFG is shown in Figure 9-61 and described in Table 9-61.

Return to the Summary Table.

This register is used to enable the subscriber 0 event and define the output policy on the selected DIO 0-15 pins.

Figure 9-61 SUB0CFG
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDINDEX
R/W-0hR/W-0h
15141312111098
RESERVEDOUTPOLICY
R/W-0hR/W-0h
76543210
RESERVEDENABLE
R/W-0hR/W-0h
Table 9-61 SUB0CFG Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16INDEXR/W0hIndicates the specific bit among lower 16 bits that is targeted by the subscriber action
0h = specific bit targeted by the subscriber action is bit0
Fh = specific bit targeted by the subscriber action is bit15
15-10RESERVEDR/W0h
9-8OUTPOLICYR/W0hThese bits configure the output policy for subscriber 0 event.
0h = Selected DIO pins are set
1h = Selected DIO pins are cleared
2h = Selected DIO pins are toggled
7-1RESERVEDR/W0h
0ENABLER/W0hThis bit is used to enable subscriber 0 event.
0h = Subscriber 0 event is disabled
1h = Subscriber 0 event is enabled

9.3.59 FILTEREN15_0 (Offset = 1508h) [Reset = 00000000h]

FILTEREN15_0 is shown in Figure 9-62 and described in Table 9-62.

Return to the Summary Table.

Programmable counter length of digital glitch filter for DIN0-DIN15

Figure 9-62 FILTEREN15_0
31302928272625242322212019181716
DIN15DIN14DIN13DIN12DIN11DIN10DIN9DIN8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
DIN7DIN6DIN5DIN4DIN3DIN2DIN1DIN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-62 FILTEREN15_0 Field Descriptions
BitFieldTypeResetDescription
31-30DIN15R/W0hProgrammable counter length of digital glitch filter for DIN15
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
29-28DIN14R/W0hProgrammable counter length of digital glitch filter for DIN14
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
27-26DIN13R/W0hProgrammable counter length of digital glitch filter for DIN13
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
25-24DIN12R/W0hProgrammable counter length of digital glitch filter for DIN12
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
23-22DIN11R/W0hProgrammable counter length of digital glitch filter for DIN11
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
21-20DIN10R/W0hProgrammable counter length of digital glitch filter for DIN10
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
19-18DIN9R/W0hProgrammable counter length of digital glitch filter for DIN9
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
17-16DIN8R/W0hProgrammable counter length of digital glitch filter for DIN8
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
15-14DIN7R/W0hProgrammable counter length of digital glitch filter for DIN7
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
13-12DIN6R/W0hProgrammable counter length of digital glitch filter for DIN6
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
11-10DIN5R/W0hProgrammable counter length of digital glitch filter for DIN5
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
9-8DIN4R/W0hProgrammable counter length of digital glitch filter for DIN4
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
7-6DIN3R/W0hProgrammable counter length of digital glitch filter for DIN3
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
5-4DIN2R/W0hProgrammable counter length of digital glitch filter for DIN2
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
3-2DIN1R/W0hProgrammable counter length of digital glitch filter for DIN1
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
1-0DIN0R/W0hProgrammable counter length of digital glitch filter for DIN0
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample

9.3.60 FILTEREN31_16 (Offset = 150Ch) [Reset = 00000000h]

FILTEREN31_16 is shown in Figure 9-63 and described in Table 9-63.

Return to the Summary Table.

Programmable counter length of digital glitch filter for DIN16-DIN31

Figure 9-63 FILTEREN31_16
31302928272625242322212019181716
DIN31DIN30DIN29DIN28DIN27DIN26DIN25DIN24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
DIN23DIN22DIN21DIN20DIN19DIN18DIN17DIN16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-63 FILTEREN31_16 Field Descriptions
BitFieldTypeResetDescription
31-30DIN31R/W0hProgrammable counter length of digital glitch filter for DIN31
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
29-28DIN30R/W0hProgrammable counter length of digital glitch filter for DIN30
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
27-26DIN29R/W0hProgrammable counter length of digital glitch filter for DIN29
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
25-24DIN28R/W0hProgrammable counter length of digital glitch filter for DIN28
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
23-22DIN27R/W0hProgrammable counter length of digital glitch filter for DIN27
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
21-20DIN26R/W0hProgrammable counter length of digital glitch filter for DIN26
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
19-18DIN25R/W0hProgrammable counter length of digital glitch filter for DIN25
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
17-16DIN24R/W0hProgrammable counter length of digital glitch filter for DIN24
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
15-14DIN23R/W0hProgrammable counter length of digital glitch filter for DIN23
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
13-12DIN22R/W0hProgrammable counter length of digital glitch filter for DIN22
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
11-10DIN21R/W0hProgrammable counter length of digital glitch filter for DIN21
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
9-8DIN20R/W0hProgrammable counter length of digital glitch filter for DIN20
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
7-6DIN19R/W0hProgrammable counter length of digital glitch filter for DIN19
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
5-4DIN18R/W0hProgrammable counter length of digital glitch filter for DIN18
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
3-2DIN17R/W0hProgrammable counter length of digital glitch filter for DIN17
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample
1-0DIN16R/W0hProgrammable counter length of digital glitch filter for DIN16
0h = No additional filter beyond the CDC synchronization sample
1h = 1 ULPCLK minimum sample
2h = 3 ULPCLK minimum sample
3h = 8 ULPCLK minimum sample

9.3.61 DMAMASK (Offset = 1510h) [Reset = 00000000h]

DMAMASK is shown in Figure 9-64 and described in Table 9-64.

Return to the Summary Table.

DMA MASK which indicates which bit lanes the DMA is allowed to modify.

Figure 9-64 DMAMASK
3130292827262524
DOUT31DOUT30DOUT29DOUT28DOUT27DOUT26DOUT25DOUT24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
DOUT23DOUT22DOUT21DOUT20DOUT19DOUT18DOUT17DOUT16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
DOUT15DOUT14DOUT13DOUT12DOUT11DOUT10DOUT9DOUT8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DOUT7DOUT6DOUT5DOUT4DOUT3DOUT2DOUT1DOUT0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-64 DMAMASK Field Descriptions
BitFieldTypeResetDescription
31DOUT31R/W0hDMA is allowed to modify DOUT31
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
30DOUT30R/W0hDMA is allowed to modify DOUT30
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
29DOUT29R/W0hDMA is allowed to modify DOUT29
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
28DOUT28R/W0hDMA is allowed to modify DOUT28
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
27DOUT27R/W0hDMA is allowed to modify DOUT27
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
26DOUT26R/W0hDMA is allowed to modify DOUT26
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
25DOUT25R/W0hDMA is allowed to modify DOUT25
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
24DOUT24R/W0hDMA is allowed to modify DOUT24
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
23DOUT23R/W0hDMA is allowed to modify DOUT23
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
22DOUT22R/W0hDMA is allowed to modify DOUT22
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
21DOUT21R/W0hDMA is allowed to modify DOUT21
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
20DOUT20R/W0hDMA is allowed to modify DOUT20
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
19DOUT19R/W0hDMA is allowed to modify DOUT19
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
18DOUT18R/W0hDMA is allowed to modify DOUT18
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
17DOUT17R/W0hDMA is allowed to modify DOUT17
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
16DOUT16R/W0hDMA is allowed to modify DOUT16
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
15DOUT15R/W0hDMA is allowed to modify DOUT15
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
14DOUT14R/W0hDMA is allowed to modify DOUT14
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
13DOUT13R/W0hDMA is allowed to modify DOUT13
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
12DOUT12R/W0hDMA is allowed to modify DOUT12
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
11DOUT11R/W0hDMA is allowed to modify DOUT11
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
10DOUT10R/W0hDMA is allowed to modify DOUT10
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
9DOUT9R/W0hDMA is allowed to modify DOUT9
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
8DOUT8R/W0hDMA is allowed to modify DOUT8
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
7DOUT7R/W0hDMA is allowed to modify DOUT7
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
6DOUT6R/W0hDMA is allowed to modify DOUT6
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
5DOUT5R/W0hDMA is allowed to modify DOUT5
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
4DOUT4R/W0hDMA is allowed to modify DOUT4
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
3DOUT3R/W0hDMA is allowed to modify DOUT3
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
2DOUT2R/W0hDMA is allowed to modify DOUT2
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
1DOUT1R/W0hDMA is allowed to modify DOUT1
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane
0DOUT0R/W0hDMA is allowed to modify DOUT0
0h = DMA is not allowed to modify this bit lane
1h = DMA is allowed to modify this bit lane

9.3.62 SUB1CFG (Offset = 1520h) [Reset = 00000000h]

SUB1CFG is shown in Figure 9-65 and described in Table 9-65.

Return to the Summary Table.

This register is used to enable the subscriber 1 event and define the output policy on the selected DIO 16-31 pins.

Figure 9-65 SUB1CFG
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVEDINDEX
R/W-0hR/W-0h
15141312111098
RESERVEDOUTPOLICY
R/W-0hR/W-0h
76543210
RESERVEDENABLE
R/W-0hR/W-0h
Table 9-65 SUB1CFG Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16INDEXR/W0hindicates the specific bit in the upper 16 bits that is targeted by the subscriber action
0h = specific bit targeted by the subscriber action is bit16
Fh = specific bit targeted by the subscriber action is bit31
15-10RESERVEDR/W0h
9-8OUTPOLICYR/W0hThese bits configure the output policy for subscriber 1 event.
0h = Selected DIO pins are set
1h = Selected DIO pins are cleared
2h = Selected DIO pins are toggled
7-1RESERVEDR/W0h
0ENABLER/W0hThis bit is used to enable subscriber 1 event.
0h = Subscriber 1 event is disabled
1h = Subscriber 1 event is enabled