SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

1.6.1 FACTORYREGION Registers

Table 1-36 lists the memory-mapped registers for the FACTORYREGION registers. All register offset addresses not listed in Table 1-36 should be considered as reserved locations and the register contents should not be modified.

Table 1-36 FACTORYREGION Registers
OffsetAcronymRegister NameGroupSection
41C40000hTRACEIDTrace identifierGo
41C40004hDEVICEIDDevice identifierGo
41C40008hUSERIDDevice variant identifierGo
41C4000ChBSLPIN_UARTGo
41C40010hBSLPIN_I2CGo
41C40014hBSLPIN_INVOKEGo
41C40018hSRAMFLASHGo
41C4001ChPLLSTARTUP0_4_8MHZGo
41C40020hPLLSTARTUP1_4_8MHZSystem PLL Parameter 1 MMR --- Data from Flash Table LookupGo
41C40024hPLLSTARTUP0_8_16MHZGo
41C40028hPLLSTARTUP1_8_16MHZSystem PLL Parameter 1 MMR --- Data from Flash Table LookupGo
41C4002ChPLLSTARTUP0_16_32MHZGo
41C40030hPLLSTARTUP1_16_32MHZSystem PLL Parameter 1 MMR --- Data from Flash Table LookupGo
41C40034hPLLSTARTUP0_32_48MHZGo
41C40038hPLLSTARTUP1_32_48MHZSystem PLL Parameter 1 MMR --- Data from Flash Table LookupGo
41C4003ChTEMP_SENSE0Temperature sensor room temperature calibration code.
This is ADC conversion results of temperature sensor output voltage.
Included in BOOTCRC calculation.
Go
41C40040hRESERVED0Go
41C40044hRESERVED1Go
41C40048hRESERVED2Go
41C4004ChRESERVED3Go
41C40050hRESERVED4Go
41C40054hRESERVED5Go
41C40058hRESERVED6Go
41C4005ChRESERVED7Go
41C40060hRESERVED8Go
41C40064hRESERVED9Go
41C40068hRESERVED10Go
41C4006ChRESERVED11Go
41C40070hRESERVED12Go
41C40074hRESERVED13Go
41C40078hRESERVED14Go
41C4007ChBOOTCRCBOOTCRC records the 32-bit CRC of all locations in OPEN including reserved locations.Go

Complex bit access types are encoded to fit into small table cells. Table 1-37 shows the codes that are used for access types in this section.

Table 1-37 FACTORYREGION Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

1.6.1.1 TRACEID (Offset = 41C40000h) [Reset = 00000000h]

TRACEID is shown in Figure 1-29 and described in Table 1-38.

Return to the Summary Table.

Unique value per device shipped

Figure 1-29 TRACEID
313029282726252423222120191817161514131211109876543210
DATA
R-
Table 1-38 TRACEID Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0h

1.6.1.2 DEVICEID (Offset = 41C40004h) [Reset = 0BB8802Fh]

DEVICEID is shown in Figure 1-30 and described in Table 1-39.

Return to the Summary Table.

Device identifier (die revision specific)

Figure 1-30 DEVICEID
3130292827262524
VERSIONPARTNUM
R-0hR-BB88h
2322212019181716
PARTNUM
R-BB88h
15141312111098
PARTNUMMANUFACTURER
R-BB88hR-17h
76543210
MANUFACTURERALWAYS_1
R-17hR-1h
Table 1-39 DEVICEID Field Descriptions
BitFieldTypeResetDescription
31-28VERSIONR0hRevision of the device
27-12PARTNUMRBB88hPart number of the device
11-1MANUFACTURERR17hTI's JEDEC bank and company code
0ALWAYS_1R1hThis is always 1

1.6.1.3 USERID (Offset = 41C40008h) [Reset = 80000000h]

USERID is shown in Figure 1-31 and described in Table 1-40.

Return to the Summary Table.

per Connectivity format, defines the variant feature set

Figure 1-31 USERID
3130292827262524
STARTMAJORREVMINORREV
R-1hR-R-
2322212019181716
VARIANT
R-
15141312111098
PART
R-
76543210
PART
R-
Table 1-40 USERID Field Descriptions
BitFieldTypeResetDescription
31STARTR1h
30-28MAJORREVR0hMonotonic increasing value indicating a new revision of the SKU significant enough that users of the device may have to revise PCB or software design
27-24MINORREVR0hMonotonic increasing value indicating a new revision of the SKU that preserves compatibility with lesser minor rev values. New capability may be introduced such that lesser minor rev numbers may not be compatible with greater if the new capability is used.
23-16VARIANTR0hBit pattern uniquely identifying the variant of a part
15-0PARTR0hBit pattern that uniquely identifying a part

1.6.1.4 BSLPIN_UART (Offset = 41C4000Ch) [Reset = 02180219h]

BSLPIN_UART is shown in Figure 1-32 and described in Table 1-41.

Return to the Summary Table.

Figure 1-32 BSLPIN_UART
31302928272625242322212019181716
UART_TXT_PFUART_TXD_PAD
R-2hR-18h
1514131211109876543210
UART_RXD_PFUART_RXD_PAD
R-2hR-19h
Table 1-41 BSLPIN_UART Field Descriptions
BitFieldTypeResetDescription
31-24UART_TXT_PFR2h
23-16UART_TXD_PADR18h
15-8UART_RXD_PFR2h
7-0UART_RXD_PADR19h

1.6.1.5 BSLPIN_I2C (Offset = 41C40010h) [Reset = 03020301h]

BSLPIN_I2C is shown in Figure 1-33 and described in Table 1-42.

Return to the Summary Table.

Figure 1-33 BSLPIN_I2C
31302928272625242322212019181716
I2C_SCL_PFI2C_SCL_PAD
R-3hR-2h
1514131211109876543210
I2C_SDA_PFI2C_SDA_PAD
R-3hR-1h
Table 1-42 BSLPIN_I2C Field Descriptions
BitFieldTypeResetDescription
31-24I2C_SCL_PFR3h
23-16I2C_SCL_PADR2h
15-8I2C_SDA_PFR3h
7-0I2C_SDA_PADR1h

1.6.1.6 BSLPIN_INVOKE (Offset = 41C40014h) [Reset = 000001ABh]

BSLPIN_INVOKE is shown in Figure 1-34 and described in Table 1-43.

Return to the Summary Table.

Figure 1-34 BSLPIN_INVOKE
3130292827262524
RESERVED
R-
2322212019181716
RESERVED
R-
15141312111098
GPIO_REG_SELGPIO_PIN_SEL
R-R-1h
76543210
GPIO_LEVELBSL_PAD
R-1hR-2Bh
Table 1-43 BSLPIN_INVOKE Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-14GPIO_REG_SELR0h
13-8GPIO_PIN_SELR1h
7GPIO_LEVELR1h
6-0BSL_PADR2Bh

1.6.1.7 SRAMFLASH (Offset = 41C40018h) [Reset = 00200080h]

SRAMFLASH is shown in Figure 1-35 and described in Table 1-44.

Return to the Summary Table.

Figure 1-35 SRAMFLASH
3130292827262524
DATAFLASH_SZSRAM_SZ
R-0hR-20h
2322212019181716
SRAM_SZ
R-20h
15141312111098
RESERVEDMAINNUMBANKSMAINFLASH_SZ
R-R-0hR-80h
76543210
MAINFLASH_SZ
R-80h
Table 1-44 SRAMFLASH Field Descriptions
BitFieldTypeResetDescription
31-26DATAFLASH_SZR0hThe encoding of the field is that the value of the field is an integer to be interpreted as number of KB.
For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on.
25-16SRAM_SZR20hThe encoding of the field is that the value of the field is an integer to be interpreted as number of KB. For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on.
15-14RESERVEDR0h
13-12MAINNUMBANKSR0h
11-0MAINFLASH_SZR80hThe encoding of the field is that the value of the field is an integer to be interpreted as number of KB. For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on.

1.6.1.8 PLLSTARTUP0_4_8MHZ (Offset = 41C4001Ch) [Reset = 00004496h]

PLLSTARTUP0_4_8MHZ is shown in Figure 1-36 and described in Table 1-45.

Return to the Summary Table.

Figure 1-36 PLLSTARTUP0_4_8MHZ
3130292827262524
RESERVED
R-
2322212019181716
CAPBOVERRIDECAPBVALCPCURRENT
R/W-R/W-R/W-4h
15141312111098
CPCURRENTSTARTTIMELP
R/W-4hR/W-12h
76543210
STARTTIMELPSTARTTIME
R/W-12hR/W-16h
Table 1-45 PLLSTARTUP0_4_8MHZ Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23CAPBOVERRIDER/W0hOverride Enable For Cap B
0h = 0
1h = 1
22-18CAPBVALR/W0hOverride Value for Cap B
17-12CPCURRENTR/W4hCharge Pump Current
11-6STARTTIMELPR/W12hStartup time from Low Power Exit to Locked Clock in resolution of 1usec
5-0STARTTIMER/W16hStartup time from Enable to Locked Clock in resolution of 1usec

1.6.1.9 PLLSTARTUP1_4_8MHZ (Offset = 41C40020h) [Reset = 0000805Ch]

PLLSTARTUP1_4_8MHZ is shown in Figure 1-37 and described in Table 1-46.

Return to the Summary Table.

Figure 1-37 PLLSTARTUP1_4_8MHZ
31302928272625242322212019181716
RESERVEDLPFRESC
R-R/W-1h
1514131211109876543210
LPFRESCLPFRESALPFCAPA
R/W-1hR/W-2hR/W-1Ch
Table 1-46 PLLSTARTUP1_4_8MHZ Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-15LPFRESCR/W1hLoop Filter Res C
14-5LPFRESAR/W2hLoop Filter Res A
4-0LPFCAPAR/W1ChLoop Filter Cap A

1.6.1.10 PLLSTARTUP0_8_16MHZ (Offset = 41C40024h) [Reset = 000052CFh]

PLLSTARTUP0_8_16MHZ is shown in Figure 1-38 and described in Table 1-47.

Return to the Summary Table.

Figure 1-38 PLLSTARTUP0_8_16MHZ
3130292827262524
RESERVED
R-
2322212019181716
CAPBOVERRIDECAPBVALCPCURRENT
R/W-R/W-R/W-5h
15141312111098
CPCURRENTSTARTTIMELP
R/W-5hR/W-Bh
76543210
STARTTIMELPSTARTTIME
R/W-BhR/W-Fh
Table 1-47 PLLSTARTUP0_8_16MHZ Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23CAPBOVERRIDER/W0hOverride Enable For Cap B
0h = 0
1h = 1
22-18CAPBVALR/W0hOverride Value for Cap B
17-12CPCURRENTR/W5hCharge Pump Current
11-6STARTTIMELPR/WBhStartup time from Low Power Exit to Locked Clock in resolution of 1usec
5-0STARTTIMER/WFhStartup time from Enable to Locked Clock in resolution of 1usec

1.6.1.11 PLLSTARTUP1_8_16MHZ (Offset = 41C40028h) [Reset = 00008030h]

PLLSTARTUP1_8_16MHZ is shown in Figure 1-39 and described in Table 1-48.

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Figure 1-39 PLLSTARTUP1_8_16MHZ
31302928272625242322212019181716
RESERVEDLPFRESC
R-R/W-1h
1514131211109876543210
LPFRESCLPFRESALPFCAPA
R/W-1hR/W-1hR/W-10h
Table 1-48 PLLSTARTUP1_8_16MHZ Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-15LPFRESCR/W1hLoop Filter Res C
14-5LPFRESAR/W1hLoop Filter Res A
4-0LPFCAPAR/W10hLoop Filter Cap A

1.6.1.12 PLLSTARTUP0_16_32MHZ (Offset = 41C4002Ch) [Reset = 0000520Ch]

PLLSTARTUP0_16_32MHZ is shown in Figure 1-40 and described in Table 1-49.

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Figure 1-40 PLLSTARTUP0_16_32MHZ
3130292827262524
RESERVED
R-
2322212019181716
CAPBOVERRIDECAPBVALCPCURRENT
R/W-R/W-R/W-5h
15141312111098
CPCURRENTSTARTTIMELP
R/W-5hR/W-8h
76543210
STARTTIMELPSTARTTIME
R/W-8hR/W-Ch
Table 1-49 PLLSTARTUP0_16_32MHZ Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23CAPBOVERRIDER/W0hOverride Enable For Cap B
0h = 0
1h = 1
22-18CAPBVALR/W0hOverride Value for Cap B
17-12CPCURRENTR/W5hCharge Pump Current
11-6STARTTIMELPR/W8hStartup time from Low Power Exit to Locked Clock in resolution of 1usec
5-0STARTTIMER/WChStartup time from Enable to Locked Clock in resolution of 1usec

1.6.1.13 PLLSTARTUP1_16_32MHZ (Offset = 41C40030h) [Reset = 00008030h]

PLLSTARTUP1_16_32MHZ is shown in Figure 1-41 and described in Table 1-50.

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Figure 1-41 PLLSTARTUP1_16_32MHZ
31302928272625242322212019181716
RESERVEDLPFRESC
R-R/W-1h
1514131211109876543210
LPFRESCLPFRESALPFCAPA
R/W-1hR/W-1hR/W-10h
Table 1-50 PLLSTARTUP1_16_32MHZ Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-15LPFRESCR/W1hLoop Filter Res C
14-5LPFRESAR/W1hLoop Filter Res A
4-0LPFCAPAR/W10hLoop Filter Cap A

1.6.1.14 PLLSTARTUP0_32_48MHZ (Offset = 41C40034h) [Reset = 0000518Ah]

PLLSTARTUP0_32_48MHZ is shown in Figure 1-42 and described in Table 1-51.

Return to the Summary Table.

Figure 1-42 PLLSTARTUP0_32_48MHZ
3130292827262524
RESERVED
R-
2322212019181716
CAPBOVERRIDECAPBVALCPCURRENT
R/W-R/W-R/W-5h
15141312111098
CPCURRENTSTARTTIMELP
R/W-5hR/W-6h
76543210
STARTTIMELPSTARTTIME
R/W-6hR/W-Ah
Table 1-51 PLLSTARTUP0_32_48MHZ Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23CAPBOVERRIDER/W0hOverride Enable For Cap B
0h = 0
1h = 1
22-18CAPBVALR/W0hOverride Value for Cap B
17-12CPCURRENTR/W5hCharge Pump Current
11-6STARTTIMELPR/W6hStartup time from Low Power Exit to Locked Clock in resolution of 1usec
5-0STARTTIMER/WAhStartup time from Enable to Locked Clock in resolution of 1usec

1.6.1.15 PLLSTARTUP1_32_48MHZ (Offset = 41C40038h) [Reset = 00008030h]

PLLSTARTUP1_32_48MHZ is shown in Figure 1-43 and described in Table 1-52.

Return to the Summary Table.

Figure 1-43 PLLSTARTUP1_32_48MHZ
31302928272625242322212019181716
RESERVEDLPFRESC
R-R/W-1h
1514131211109876543210
LPFRESCLPFRESALPFCAPA
R/W-1hR/W-1hR/W-10h
Table 1-52 PLLSTARTUP1_32_48MHZ Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h
22-15LPFRESCR/W1hLoop Filter Res C
14-5LPFRESAR/W1hLoop Filter Res A
4-0LPFCAPAR/W10hLoop Filter Cap A

1.6.1.16 TEMP_SENSE0 (Offset = 41C4003Ch) [Reset = 00000000h]

TEMP_SENSE0 is shown in Figure 1-44 and described in Table 1-53.

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Temperature sensor room temperature calibration code. This is ADC conversion results of temperature sensor output voltage. Included in BOOTCRC calculation.

Figure 1-44 TEMP_SENSE0
313029282726252423222120191817161514131211109876543210
DATA
R-
Table 1-53 TEMP_SENSE0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0h

1.6.1.17 RESERVED0 (Offset = 41C40040h) [Reset = 00000000h]

RESERVED0 is shown in Figure 1-45 and described in Table 1-54.

Return to the Summary Table.

Figure 1-45 RESERVED0
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-54 RESERVED0 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.18 RESERVED1 (Offset = 41C40044h) [Reset = 00000000h]

RESERVED1 is shown in Figure 1-46 and described in Table 1-55.

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Figure 1-46 RESERVED1
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-55 RESERVED1 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.19 RESERVED2 (Offset = 41C40048h) [Reset = 00000000h]

RESERVED2 is shown in Figure 1-47 and described in Table 1-56.

Return to the Summary Table.

Figure 1-47 RESERVED2
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-56 RESERVED2 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.20 RESERVED3 (Offset = 41C4004Ch) [Reset = 00000000h]

RESERVED3 is shown in Figure 1-48 and described in Table 1-57.

Return to the Summary Table.

Figure 1-48 RESERVED3
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-57 RESERVED3 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.21 RESERVED4 (Offset = 41C40050h) [Reset = 00000000h]

RESERVED4 is shown in Figure 1-49 and described in Table 1-58.

Return to the Summary Table.

Figure 1-49 RESERVED4
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-58 RESERVED4 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.22 RESERVED5 (Offset = 41C40054h) [Reset = 00000000h]

RESERVED5 is shown in Figure 1-50 and described in Table 1-59.

Return to the Summary Table.

Figure 1-50 RESERVED5
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-59 RESERVED5 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.23 RESERVED6 (Offset = 41C40058h) [Reset = 00000000h]

RESERVED6 is shown in Figure 1-51 and described in Table 1-60.

Return to the Summary Table.

Figure 1-51 RESERVED6
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-60 RESERVED6 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.24 RESERVED7 (Offset = 41C4005Ch) [Reset = 00000000h]

RESERVED7 is shown in Figure 1-52 and described in Table 1-61.

Return to the Summary Table.

Figure 1-52 RESERVED7
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-61 RESERVED7 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.25 RESERVED8 (Offset = 41C40060h) [Reset = 00000000h]

RESERVED8 is shown in Figure 1-53 and described in Table 1-62.

Return to the Summary Table.

Figure 1-53 RESERVED8
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-62 RESERVED8 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.26 RESERVED9 (Offset = 41C40064h) [Reset = 00000000h]

RESERVED9 is shown in Figure 1-54 and described in Table 1-63.

Return to the Summary Table.

Figure 1-54 RESERVED9
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-63 RESERVED9 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.27 RESERVED10 (Offset = 41C40068h) [Reset = 00000000h]

RESERVED10 is shown in Figure 1-55 and described in Table 1-64.

Return to the Summary Table.

Figure 1-55 RESERVED10
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-64 RESERVED10 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.28 RESERVED11 (Offset = 41C4006Ch) [Reset = 00000000h]

RESERVED11 is shown in Figure 1-56 and described in Table 1-65.

Return to the Summary Table.

Figure 1-56 RESERVED11
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-65 RESERVED11 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.29 RESERVED12 (Offset = 41C40070h) [Reset = 00000000h]

RESERVED12 is shown in Figure 1-57 and described in Table 1-66.

Return to the Summary Table.

Figure 1-57 RESERVED12
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-66 RESERVED12 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.30 RESERVED13 (Offset = 41C40074h) [Reset = 00000000h]

RESERVED13 is shown in Figure 1-58 and described in Table 1-67.

Return to the Summary Table.

Figure 1-58 RESERVED13
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-67 RESERVED13 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.31 RESERVED14 (Offset = 41C40078h) [Reset = 00000000h]

RESERVED14 is shown in Figure 1-59 and described in Table 1-68.

Return to the Summary Table.

Figure 1-59 RESERVED14
313029282726252423222120191817161514131211109876543210
RESERVED
R-0h
Table 1-68 RESERVED14 Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

1.6.1.32 BOOTCRC (Offset = 41C4007Ch) [Reset = 00000000h]

BOOTCRC is shown in Figure 1-60 and described in Table 1-69.

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BOOTCRC records the 32-bit CRC of all locations in OPEN including reserved locations.

Figure 1-60 BOOTCRC
313029282726252423222120191817161514131211109876543210
DATA
R-
Table 1-69 BOOTCRC Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0h