SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

21 MCAN Registers

Table 21-1 lists the memory-mapped registers for the MCAN registers. All register offset addresses not listed in Table 21-1 should be considered as reserved locations and the register contents should not be modified.

Table 21-1 MCAN Registers
Offset Acronym Register Name Group Section
6004h CANRX CAN RX IO Go
6008h CANTX CAN TX IO Go
6204h CANRX FUPDATE version of CANRX Go
6208h CANTX FUPDATE version of CANTX Go
6480h CPU_CONNECT_0 CPU Connect Go
6800h PWREN Power enable Go
6804h RSTCTL Reset Control Go
6814h STAT Status Register Go
7000h MCAN_CREL MCAN Core Release Register Go
7004h MCAN_ENDN MCAN Endian Register Go
700Ch MCAN_DBTP MCAN Data Bit Timing and Prescaler Register Go
7010h MCAN_TEST MCAN Test Register Go
7014h MCAN_RWD MCAN RAM Watchdog Go
7018h MCAN_CCCR MCAN CC Control Register Go
701Ch MCAN_NBTP MCAN Nominal Bit Timing and Prescaler Register Go
7020h MCAN_TSCC MCAN Timestamp Counter Configuration Go
7024h MCAN_TSCV MCAN Timestamp Counter Value Go
7028h MCAN_TOCC MCAN Timeout Counter Configuration Go
702Ch MCAN_TOCV MCAN Timeout Counter Value Go
7040h MCAN_ECR MCAN Error Counter Register Go
7044h MCAN_PSR MCAN Protocol Status Register Go
7048h MCAN_TDCR MCAN Transmitter Delay Compensation Register Go
7050h MCAN_IR MCAN Interrupt Register Go
7054h MCAN_IE MCAN Interrupt Enable Go
7058h MCAN_ILS MCAN Interrupt Line Select Go
705Ch MCAN_ILE MCAN Interrupt Line Enable Go
7080h MCAN_GFC MCAN Global Filter Configuration Go
7084h MCAN_SIDFC MCAN Standard ID Filter Configuration Go
7088h MCAN_XIDFC MCAN Extended ID Filter Configuration Go
7090h MCAN_XIDAM MCAN Extended ID and Mask Go
7094h MCAN_HPMS MCAN High Priority Message Status Go
7098h MCAN_NDAT1 MCAN New Data 1 Go
709Ch MCAN_NDAT2 MCAN New Data 2 Go
70A0h MCAN_RXF0C MCAN Rx FIFO 0 Configuration Go
70A4h MCAN_RXF0S MCAN Rx FIFO 0 Status Go
70A8h MCAN_RXF0A MCAN Rx FIFO 0 Acknowledge Go
70ACh MCAN_RXBC MCAN Rx Buffer Configuration Go
70B0h MCAN_RXF1C MCAN Rx FIFO 1 Configuration Go
70B4h MCAN_RXF1S MCAN Rx FIFO 1 Status Go
70B8h MCAN_RXF1A MCAN Rx FIFO 1 Acknowledge Go
70BCh MCAN_RXESC MCAN Rx Buffer / FIFO Element Size Configuration Go
70C0h MCAN_TXBC MCAN Tx Buffer Configuration Go
70C4h MCAN_TXFQS MCAN Tx FIFO / Queue Status Go
70C8h MCAN_TXESC MCAN Tx Buffer Element Size Configuration Go
70CCh MCAN_TXBRP MCAN Tx Buffer Request Pending Go
70D0h MCAN_TXBAR MCAN Tx Buffer Add Request Go
70D4h MCAN_TXBCR MCAN Tx Buffer Cancellation Request Go
70D8h MCAN_TXBTO MCAN Tx Buffer Transmission Occurred Go
70DCh MCAN_TXBCF MCAN Tx Buffer Cancellation Finished Go
70E0h MCAN_TXBTIE MCAN Tx Buffer Transmission Interrupt Enable Go
70E4h MCAN_TXBCIE MCAN Tx Buffer Cancellation Finished Interrupt Enable Go
70F0h MCAN_TXEFC MCAN Tx Event FIFO Configuration Go
70F4h MCAN_TXEFS MCAN Tx Event FIFO Status Go
70F8h MCAN_TXEFA MCAN Tx Event FIFO Acknowledge Go
7200h MCANSS_PID MCAN Subsystem Revision Register Go
7204h MCANSS_CTRL MCAN Subsystem Control Register Go
7208h MCANSS_STAT MCAN Subsystem Status Register Go
720Ch MCANSS_ICS MCAN Subsystem Interrupt Clear Shadow Register Go
7210h MCANSS_IRS MCAN Subsystem Interrupt Raw Satus Register Go
7214h MCANSS_IECS MCAN Subsystem Interrupt Enable Clear Shadow Register Go
7218h MCANSS_IE MCAN Subsystem Interrupt Enable Register Go
721Ch MCANSS_IES MCAN Subsystem Interrupt Enable Status Go
7220h MCANSS_EOI MCAN Subsystem End of Interrupt Go
7224h MCANSS_EXT_TS_PRESCALER MCAN Subsystem External Timestamp Prescaler 0 Go
7228h MCANSS_EXT_TS_UNSERVICED_INTR_CNTR MCAN Subsystem External Timestamp Unserviced Interrupts Counter Go
7400h MCANERR_REV MCAN Error Aggregator Revision Register Go
7408h MCANERR_VECTOR MCAN ECC Vector Register Go
740Ch MCANERR_STAT MCAN Error Misc Status Go
7410h MCANERR_WRAP_REV MCAN ECC Wrapper Revision Register Go
7414h MCANERR_CTRL MCAN ECC Control Go
7418h MCANERR_ERR_CTRL1 MCAN ECC Error Control 1 Register Go
741Ch MCANERR_ERR_CTRL2 MCAN ECC Error Control 2 Register Go
7420h MCANERR_ERR_STAT1 MCAN ECC Error Status 1 Register Go
7424h MCANERR_ERR_STAT2 MCAN ECC Error Status 2 Register Go
7428h MCANERR_ERR_STAT3 MCAN ECC Error Status 3 Register Go
743Ch MCANERR_SEC_EOI MCAN Single Error Corrected End of Interrupt Register Go
7440h MCANERR_SEC_STATUS MCAN Single Error Corrected Interrupt Status Register Go
7480h MCANERR_SEC_ENABLE_SET MCAN Single Error Corrected Interrupt Enable Set Register Go
74C0h MCANERR_SEC_ENABLE_CLR MCAN Single Error Corrected Interrupt Enable Clear Register Go
753Ch MCANERR_DED_EOI MCAN Double Error Detected End of Interrupt Register Go
7540h MCANERR_DED_STATUS MCAN Double Error Detected Interrupt Status Register Go
7580h MCANERR_DED_ENABLE_SET MCAN Double Error Detected Interrupt Enable Set Register Go
75C0h MCANERR_DED_ENABLE_CLR MCAN Double Error Detected Interrupt Enable Clear Register Go
7600h MCANERR_AGGR_ENABLE_SET MCAN Error Aggregator Enable Set Register Go
7604h MCANERR_AGGR_ENABLE_CLR MCAN Error Aggregator Enable Clear Register Go
7608h MCANERR_AGGR_STATUS_SET MCAN Error Aggregator Status Set Register Go
760Ch MCANERR_AGGR_STATUS_CLR MCAN Error Aggregator Status Clear Register Go
7820h IIDX Interrupt Index Register CPU_INT Go
7828h IMASK Interrupt mask CPU_INT Go
7830h RIS Raw interrupt status CPU_INT Go
7838h MIS Masked interrupt status CPU_INT Go
7840h ISET Interrupt set CPU_INT Go
7848h ICLR Interrupt clear CPU_INT Go
78E0h EVT_MODE Event Mode Go
78FCh DESC Module Description Go
7900h MCANSS_CLKEN MCAN module clock enable Go
7904h MCANSS_CLKDIV Clock divider Go
7908h MCANSS_CLKCTL MCAN-SS clock stop control register Go
790Ch MCANSS_CLKSTS MCANSS clock stop status register Go

Complex bit access types are encoded to fit into small table cells. Table 21-2 shows the codes that are used for access types in this section.

Table 21-2 MCAN Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R
-0		 Read
Returns 0s
RC R
C		 Read
to Clear
RS R
S		 Read
to Set
Write Type
W W Write
W1C W
1C		 Write
1 to clear
W1S W
1S		 Write
1 to set
W1SQ W
1S
Q		 Write
1 to set
Qualified. A condition must be met for this operation to occur.
WD W
D		 Write
Decrement. Decrements the specified bit field by the amount written.
WI W
I		 Write
Increment. Increments the specified bit field by the amount written.
WK W
K		 Write
Write protected by a key
WQ W
Q		 Write
Qualified. A condition must be met for this operation to occur.
Reset or Default Value
-n Value after reset or the default value

21.1 CANRX (Offset = 6004h) [Reset = 00000000h]

CANRX is shown in Figure 21-1 and described in Table 21-3.

Return to the Summary Table.

CAN RX IO

Figure 21-1 CANRX
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R-0h
Table 21-3 CANRX Field Descriptions
Bit Field Type Reset Description
31 RESERVED R 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R 0h

21.2 CANTX (Offset = 6008h) [Reset = 00000000h]

CANTX is shown in Figure 21-2 and described in Table 21-4.

Return to the Summary Table.

CAN TX IO

Figure 21-2 CANTX
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R-0h
Table 21-4 CANTX Field Descriptions
Bit Field Type Reset Description
31 RESERVED R 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R 0h

21.3 CANRX (Offset = 6204h) [Reset = 00000000h]

CANRX is shown in Figure 21-3 and described in Table 21-5.

Return to the Summary Table.

FUPDATE version of CANRX

Figure 21-3 CANRX
31 30 29 28 27 26 25 24
RESERVED IOADDR
R-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 21-5 CANRX Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED R 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

21.4 CANTX (Offset = 6208h) [Reset = 00000000h]

CANTX is shown in Figure 21-4 and described in Table 21-6.

Return to the Summary Table.

FUPDATE version of CANTX

Figure 21-4 CANTX
31 30 29 28 27 26 25 24
RESERVED IOADDR
R-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 21-6 CANTX Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED R 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update

0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

21.5 CPU_CONNECT_0 (Offset = 6480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 21-5 and described in Table 21-7.

Return to the Summary Table.

Directly connect peripheral publisher port to application processor

Figure 21-5 CPU_CONNECT_0
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CPUSS0_CONN RESERVED
R-0h R/W-0h R-0h
Table 21-7 CPU_CONNECT_0 Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 CPUSS0_CONN R/W 0h CPUSS0 connect bit.
0h = The CPU is not connected.
1h = The CPU is connected.
0 RESERVED R 0h

21.6 PWREN (Offset = 6800h) [Reset = 00000000h]

PWREN is shown in Figure 21-6 and described in Table 21-8.

Return to the Summary Table.

Register to control the power state

Figure 21-6 PWREN
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE
R-0h R/WK-0h
Table 21-8 PWREN Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to allow Power State Change
26h = KEY to allow write access to this register
23-1 RESERVED R 0h
0 ENABLE R/WK 0h Enable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

21.7 RSTCTL (Offset = 6804h) [Reset = 00000000h]

RSTCTL is shown in Figure 21-7 and described in Table 21-9.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 21-7 RSTCTL
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETSTKYCLR RESETASSERT
R-0h WK-0h WK-0h
Table 21-9 RSTCTL Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h Unlock key
B1h = KEY to allow write access to this register
23-2 RESERVED R 0h
1 RESETSTKYCLR WK 0h Clear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0 RESETASSERT WK 0h Assert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

21.8 STAT (Offset = 6814h) [Reset = 00000000h]

STAT is shown in Figure 21-8 and described in Table 21-10.

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peripheral enable and reset status

Figure 21-8 STAT
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED RESETSTKY
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 21-10 STAT Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 RESETSTKY R 0x0 This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0 RESERVED R 0h

21.9 MCAN_CREL (Offset = 7000h) [Reset = 32380608h]

MCAN_CREL is shown in Figure 21-9 and described in Table 21-11.

Return to the Summary Table.

MCAN Core Release Register

Figure 21-9 MCAN_CREL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL STEP SUBSTEP YEAR
R-3h R-2h R-3h R-8h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON DAY
R-6h R-8h
Table 21-11 MCAN_CREL Field Descriptions
Bit Field Type Reset Description
31-28 REL R 3h Core Release. One digit, BCD-coded.
27-24 STEP R 2h Step of Core Release. One digit, BCD-coded.
23-20 SUBSTEP R 3h Sub-Step of Core Release. One digit, BCD-coded.
19-16 YEAR R 8h Time Stamp Year. One digit, BCD-coded.
15-8 MON R 6h Time Stamp Month. Two digits, BCD-coded.
7-0 DAY R 8h Time Stamp Day. Two digits, BCD-coded.

21.10 MCAN_ENDN (Offset = 7004h) [Reset = 87654321h]

MCAN_ENDN is shown in Figure 21-10 and described in Table 21-12.

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MCAN Endian Register

Figure 21-10 MCAN_ENDN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
R-87654321h
Table 21-12 MCAN_ENDN Field Descriptions
Bit Field Type Reset Description
31-0 ETV R 87654321h Endianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU.

21.11 MCAN_DBTP (Offset = 700Ch) [Reset = 00000A33h]

MCAN_DBTP is shown in Figure 21-11 and described in Table 21-13.

Return to the Summary Table.

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq.

DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) (DTSEG1 + DTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Figure 21-11 MCAN_DBTP
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
TDC RESERVED DBRP
R/WQ-0h R-0h R/WQ-0h
15 14 13 12 11 10 9 8
RESERVED DTSEG1
R-0h R/WQ-Ah
7 6 5 4 3 2 1 0
DTSEG2 DSJW
R/WQ-3h R/WQ-3h
Table 21-13 MCAN_DBTP Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23 TDC R/WQ 0h Transmitter Delay Compensation
0 Transmitter Delay Compensation disabled
1 Transmitter Delay Compensation enabled
22-21 RESERVED R 0h
20-16 DBRP R/WQ 0h Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-13 RESERVED R 0h
12-8 DTSEG1 R/WQ Ah Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7-4 DTSEG2 R/WQ 3h Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-0 DSJW R/WQ 3h Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.12 MCAN_TEST (Offset = 7010h) [Reset = 000000X0h]

MCAN_TEST is shown in Figure 21-12 and described in Table 21-14.

Return to the Summary Table.

Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset.

Loop Back Mode and software control of the internal CAN TX pin are hardware test modes. Programming of
TX ? '00' may disturb the message transfer on the CAN bus.

Figure 21-12 MCAN_TEST
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RX TX LBCK RESERVED
R-X R/WQ-0h R/WQ-0h R-0h
Table 21-14 MCAN_TEST Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 RX R X Receive Pin. Monitors the actual value of the CAN receive pin.
0h = DOMINANT : The CAN bus is dominant (CAN RX pin = '0')
1h = RECESSIVE : The CAN bus is recessive (CAN RX pin = '1')
6-5 TX R/WQ 0h Control of Transmit Pin
00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time
01 Sample Point can be monitored at CAN TX pin
10 Dominant ('0') level at CAN TX pin
11 Recessive ('1') at CAN TX pin

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4 LBCK R/WQ 0h Loop Back Mode. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0h = DISABLE : Reset value, Loop Back Mode is disabled
1h = ENABLE : Loop Back Mode is enabled
3-0 RESERVED R 0h

21.13 MCAN_RWD (Offset = 7014h) [Reset = 00000000h]

MCAN_RWD is shown in Figure 21-13 and described in Table 21-15.

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MCAN RAM Watchdog

Figure 21-13 MCAN_RWD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WDV WDC
R-0h R-0h R/WQ-0h
Table 21-15 MCAN_RWD Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-8 WDV R 0h Watchdog Value. Acutal Message RAM Watchdog Counter Value.

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock.
7-0 WDC R/WQ 0h Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.14 MCAN_CCCR (Offset = 7018h) [Reset = 00000001h]

MCAN_CCCR is shown in Figure 21-14 and described in Table 21-16.

Return to the Summary Table.

MCAN CC Control Register

Figure 21-14 MCAN_CCCR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
NISO TXP EFBI PXHD RESERVED BRSE FDOE
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R-0h R/WQ-0h R/WQ-0h
7 6 5 4 3 2 1 0
TEST DAR MON CSR CSA ASM CCE INIT
R/W1SQ-0h R/WQ-0h R/W1SQ-0h R/W-0h R-0h R/W1SQ-0h R/WQ-0h R/W-1h
Table 21-16 MCAN_CCCR Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15 NISO R/WQ 0h Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
0 CAN FD frame format according to ISO 11898-1:2015
1 CAN FD frame format according to Bosch CAN FD Specification V1.0
14 TXP R/WQ 0h Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame.
0 Transmit pause disabled
1 Transmit pause enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
13 EFBI R/WQ 0h Edge Filtering during Bus Integration
0 Edge filtering disabled
1 Two consecutive dominant tq required to detect an edge for hard synchronization

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
12 PXHD R/WQ 0h Protocol Exception Handling Disable
0 Protocol exception handling enabled
1 Protocol exception handling disabled
Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
11-10 RESERVED R 0h
9 BRSE R/WQ 0h Bit Rate Switch Enable
0 Bit rate switching for transmissions disabled
1 Bit rate switching for transmissions enabled
Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
8 FDOE R/WQ 0h Flexible Datarate Operation Enable
0 FD operation disabled
1 FD operation enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7 TEST R/W1SQ 0h Test Mode Enable
0 Normal operation, register TEST holds reset values
1 Test Mode, write access to register TEST enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
6 DAR R/WQ 0h Disable Automatic Retransmission
0 Automatic retransmission of messages not transmitted successfully enabled
1 Automatic retransmission disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
5 MON R/W1SQ 0h Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Bus Monitoring Mode is disabled
1 Bus Monitoring Mode is enabled

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
4 CSR R/W 0h Clock Stop Request
0 No clock stop is requested
1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.
3 CSA R 0h Clock Stop Acknowledge
0 No clock stop acknowledged
1 MCAN may be set in power down by stopping the Host and CAN clocks
2 ASM R/W1SQ 0h Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time.
0 Normal CAN operation
1 Restricted Operation Mode active

Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1 CCE R/WQ 0h Configuration Change Enable
0 The CPU has no write access to the protected configuration registers
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0 INIT R/W 1h Initialization
0 Normal Operation
1 Initialization is started
Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.

21.15 MCAN_NBTP (Offset = 701Ch) [Reset = 06000A03h]

MCAN_NBTP is shown in Figure 21-15 and described in Table 21-17.

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This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq.

NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2.

Therefore the length of the bit time is (programmed values) (NTSEG1 + NTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the MCAN for a bit rate of 500 kBit/s.

Figure 21-15 MCAN_NBTP
31 30 29 28 27 26 25 24
NSJW NBRP
R/WQ-3h R/WQ-0h
23 22 21 20 19 18 17 16
NBRP
R/WQ-0h
15 14 13 12 11 10 9 8
NTSEG1
R/WQ-Ah
7 6 5 4 3 2 1 0
RESERVED NTSEG2
R-0h R/WQ-3h
Table 21-17 MCAN_NBTP Field Descriptions
Bit Field Type Reset Description
31-25 NSJW R/WQ 3h Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
24-16 NBRP R/WQ 0h Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-8 NTSEG1 R/WQ Ah Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7 RESERVED R 0h
6-0 NTSEG2 R/WQ 3h Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.16 MCAN_TSCC (Offset = 7020h) [Reset = 00000000h]

MCAN_TSCC is shown in Figure 21-16 and described in Table 21-18.

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MCAN Timestamp Counter Configuration

Figure 21-16 MCAN_TSCC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED TCP
R-0h R/WQ-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TSS
R-0h R/WQ-0h
Table 21-18 MCAN_TSCC Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h
19-16 TCP R/WQ 0h Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Note: With CAN FD an external counter is required for timestamp generation (TSS = '10').

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2 RESERVED R 0h
1-0 TSS R/WQ 0h Timestamp Select
00 Timestamp counter value always 0x0000
01 Timestamp counter value incremented according to TCP
10 External timestamp counter value used
11 Same as '00'

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.17 MCAN_TSCV (Offset = 7024h) [Reset = 00000000h]

MCAN_TSCV is shown in Figure 21-17 and described in Table 21-19.

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MCAN Timestamp Counter Value

Figure 21-17 MCAN_TSCV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TSC
R-0h R/W-0h
Table 21-19 MCAN_TSCV Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-0 TSC R/W 0h Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the External Timestamp Counter value, and a write access has no impact.

Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not
caused by write access to MCAN_TSCV.

21.18 MCAN_TOCC (Offset = 7028h) [Reset = FFFF0000h]

MCAN_TOCC is shown in Figure 21-18 and described in Table 21-20.

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MCAN Timeout Counter Configuration

Figure 21-18 MCAN_TOCC
31 30 29 28 27 26 25 24
TOP
R/WQ-FFFFh
23 22 21 20 19 18 17 16
TOP
R/WQ-FFFFh
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TOS ETOC
R-0h R/WQ-0h R/WQ-0h
Table 21-20 MCAN_TOCC Field Descriptions
Bit Field Type Reset Description
31-16 TOP R/WQ FFFFh Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-3 RESERVED R 0h
2-1 TOS R/WQ 0h Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored.
00 Continuous operation
01 Timeout controlled by Tx Event FIFO
10 Timeout controlled by Rx FIFO 0
11 Timeout controlled by Rx FIFO 1

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0 ETOC R/WQ 0h Enable Timeout Counter
0 Timeout Counter disabled
1 Timeout Counter enabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.19 MCAN_TOCV (Offset = 702Ch) [Reset = 0000FFFFh]

MCAN_TOCV is shown in Figure 21-19 and described in Table 21-21.

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MCAN Timeout Counter Value

Figure 21-19 MCAN_TOCV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TOC
R-0h R/W-FFFFh
Table 21-21 MCAN_TOCV Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-0 TOC R/W FFFFh Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.

21.20 MCAN_ECR (Offset = 7040h) [Reset = 00000000h]

MCAN_ECR is shown in Figure 21-20 and described in Table 21-22.

Return to the Summary Table.

MCAN Error Counter Register

Figure 21-20 MCAN_ECR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CEL
R-0h RC-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP REC TEC
R-0h R-0h R-0h
Table 21-22 MCAN_ECR Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-16 CEL RC 0h CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
15 RP R 0h Receive Error Passive
0 The Receive Error Counter is below the error passive level of 128
1 The Receive Error Counter has reached the error passive level of 128
14-8 REC R 0h Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
7-0 TEC R 0h Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255.

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

21.21 MCAN_PSR (Offset = 7044h) [Reset = 00000707h]

MCAN_PSR is shown in Figure 21-21 and described in Table 21-23.

Return to the Summary Table.

MCAN Protocol Status Register

Figure 21-21 MCAN_PSR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED TDCV
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED PXE RFDF RBRS RESI DLEC
R-0h RC-0h RC-0h RC-0h RC-0h RS-7h
7 6 5 4 3 2 1 0
BO EW EP ACT LEC
R-0h R-0h R-0h R-0h RS-7h
Table 21-23 MCAN_PSR Field Descriptions
Bit Field Type Reset Description
31-23 RESERVED R 0h
22-16 TDCV R 0h Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.
15 RESERVED R 0h
14 PXE RC 0h Protocol Exception Event
0 No protocol exception event occurred since last read access
1 Protocol exception event occurred
13 RFDF RC 0h Received a CAN FD Message. This bit is set independent of acceptance filtering.
0 Since this bit was reset by the CPU, no CAN FD message has been received
1 Message in CAN FD format with FDF flag set has been received
12 RBRS RC 0h BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its BRS flag set
1 Last received CAN FD message had its BRS flag set
11 RESI RC 0h ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering.
0 Last received CAN FD message did not have its ESI flag set
1 Last received CAN FD message had its ESI flag set
10-8 DLEC RS 7h Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.
7 BO R 0h Bus_Off Status
0 The M_CAN is not Bus_Off
1 The M_CAN is in Bus_Off state
6 EW R 0h Warning Status
0 Both error counters are below the Error_Warning limit of 96
1 At least one of error counter has reached the Error_Warning limit of 96
5 EP R 0h Error Passive
0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
1 The M_CAN is in the Error_Passive state
4-3 ACT R 0h Node Activity. Monitors the module's CAN communication state.
00 Synchronizing - node is synchronizing on CAN communication
01 Idle - node is neither receiver nor transmitter
10 Receiver - node is operating as receiver
11 Transmitter - node is operating as transmitter

Note: ACT is set to '00' by a Protocol Exception Event.
2-0 LEC RS 7h Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
0 No Error: No error occurred since LEC has been reset by successful reception or transmission.
1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 Form Error: A fixed format part of a received frame has the wrong format.
3 AckError: The message transmitted by the MCAN was not acknowledged by another node.
4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register.

Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences.

21.22 MCAN_TDCR (Offset = 7048h) [Reset = 00000000h]

MCAN_TDCR is shown in Figure 21-22 and described in Table 21-24.

Return to the Summary Table.

MCAN Transmitter Delay Compensation Register

Figure 21-22 MCAN_TDCR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED TDCO
R-0h R/WQ-0h
7 6 5 4 3 2 1 0
RESERVED TDCF
R-0h R/WQ-0h
Table 21-24 MCAN_TDCR Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14-8 TDCO R/WQ 0h Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7 RESERVED R 0h
6-0 TDCF R/WQ 0h Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.23 MCAN_IR (Offset = 7050h) [Reset = 80000000h]

MCAN_IR is shown in Figure 21-23 and described in Table 21-25.

Return to the Summary Table.

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. Aflag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. Ahard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled.

Figure 21-23 MCAN_IR
31 30 29 28 27 26 25 24
RESERVED ARA PED PEA WDI BO EW
R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
23 22 21 20 19 18 17 16
EP ELO BEU RESERVED DRX TOO MRAF TSW
R/W1C-0h R/W1C-0h R/W1C-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
15 14 13 12 11 10 9 8
TEFL TEFF TEFW TEFN TFE TCF TC HPM
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
RF1L RF1F RF1W RF1N RF0L RF0F RF0W RF0N
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
Table 21-25 MCAN_IR Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29 ARA R/W1C 0h Access to Reserved Address
0 No access to reserved address occurred
1 Access to reserved address occurred
28 PED R/W1C 0h Protocol Error in Data Phase (Data Bit Time is used)
0 No protocol error in data phase
1 Protocol error in data phase detected (PSR.DLEC ? 0,7)
27 PEA R/W1C 0h Protocol Error in Arbitration Phase (Nominal Bit Time is used)
0 No protocol error in arbitration phase
1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7)
26 WDI R/W1C 0h Watchdog Interrupt
0 No Message RAM Watchdog event occurred
1 Message RAM Watchdog event due to missing READY
25 BO R/W1C 0h Bus_Off Status
0 Bus_Off status unchanged
1 Bus_Off status changed
24 EW R/W1C 0h Warning Status
0 Error_Warning status unchanged
1 Error_Warning status changed
23 EP R/W1C 0h Error Passive
0 Error_Passive status unchanged
1 Error_Passive status changed
22 ELO R/W1C 0h Error Logging Overflow
0 CAN Error Logging Counter did not overflow
1 Overflow of CAN Error Logging Counter occurred
21 BEU R/W1C 0h Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
0 No bit error detected when reading from Message RAM
1 Bit error detected, uncorrected (e.g. parity logic)
20 RESERVED R 0h
19 DRX R/W1C 0h Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
0 No Rx Buffer updated
1 At least one received message stored into an Rx Buffer
18 TOO R/W1C 0h Timeout Occurred
0 No timeout
1 Timeout reached
17 MRAF R/W1C 0h Message RAM Access Failure. The flag is set, when the Rx Handler:
- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
- was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.
0 No Message RAM access failure occurred
1 Message RAM access failure occurred
16 TSW R/W1C 0h Timestamp Wraparound
0 No timestamp counter wrap-around
1 Timestamp counter wrapped around
15 TEFL R/W1C 0h Tx Event FIFO Element Lost
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero
14 TEFF R/W1C 0h Tx Event FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full
13 TEFW R/W1C 0h Tx Event FIFO Watermark Reached
0 Tx Event FIFO fill level below watermark
1 Tx Event FIFO fill level reached watermark
12 TEFN R/W1C 0h Tx Event FIFO New Entry
0 Tx Event FIFO unchanged
1 Tx Handler wrote Tx Event FIFO element
11 TFE R/W1C 0h Tx FIFO Empty
0 Tx FIFO non-empty
1 Tx FIFO empty
10 TCF R/W1C 0h Transmission Cancellation Finished
0 No transmission cancellation finished
1 Transmission cancellation finished
9 TC R/W1C 0h Transmission Completed
0 No transmission completed
1 Transmission completed
8 HPM R/W1C 0h High Priority Message
0 No high priority message received
1 High priority message received
7 RF1L R/W1C 0h Rx FIFO 1 Message Lost
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero
6 RF1F R/W1C 0h Rx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full
5 RF1W R/W1C 0h Rx FIFO 1 Watermark Reached
0 Rx FIFO 1 fill level below watermark
1 Rx FIFO 1 fill level reached watermark
4 RF1N R/W1C 0h Rx FIFO 1 New Message
0 No new message written to Rx FIFO 1
1 New message written to Rx FIFO 1
3 RF0L R/W1C 0h Rx FIFO 0 Message Lost
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
2 RF0F R/W1C 0h Rx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full
1 RF0W R/W1C 0h Rx FIFO 0 Watermark Reached
0 Rx FIFO 0 fill level below watermark
1 Rx FIFO 0 fill level reached watermark
0 RF0N R/W1C 0h Rx FIFO 0 New Message
0 No new message written to Rx FIFO 0
1 New message written to Rx FIFO 0

21.24 MCAN_IE (Offset = 7054h) [Reset = 00000000h]

MCAN_IE is shown in Figure 21-24 and described in Table 21-26.

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MCAN Interrupt Enable

Figure 21-24 MCAN_IE
31 30 29 28 27 26 25 24
RESERVED ARAE PEDE PEAE WDIE BOE EWE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
EPE ELOE BEUE BECE DRXE TOOE MRAFE TSWE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 21-26 MCAN_IE Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29 ARAE R/W 0h Access to Reserved Address Enable
28 PEDE R/W 0h Protocol Error in Data Phase Enable
27 PEAE R/W 0h Protocol Error in Arbitration Phase Enable
26 WDIE R/W 0h Watchdog Interrupt Enable
25 BOE R/W 0h Bus_Off Status Enable
24 EWE R/W 0h Warning Status Enable
23 EPE R/W 0h Error Passive Enable
22 ELOE R/W 0h Error Logging Overflow Enable
21 BEUE R/W 0h Bit Error Uncorrected Enable
20 BECE R/W 0h Bit Error Corrected Enable

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave this bit cleared to '0'.
19 DRXE R/W 0h Message Stored to Dedicated Rx Buffer Enable
18 TOOE R/W 0h Timeout Occurred Enable
17 MRAFE R/W 0h Message RAM Access Failure Enable
16 TSWE R/W 0h Timestamp Wraparound Enable
15 TEFLE R/W 0h Tx Event FIFO Element Lost Enable
14 TEFFE R/W 0h Tx Event FIFO Full Enable
13 TEFWE R/W 0h Tx Event FIFO Watermark Reached Enable
12 TEFNE R/W 0h Tx Event FIFO New Entry Enable
11 TFEE R/W 0h Tx FIFO Empty Enable
10 TCFE R/W 0h Transmission Cancellation Finished Enable
9 TCE R/W 0h Transmission Completed Enable
8 HPME R/W 0h High Priority Message Enable
7 RF1LE R/W 0h Rx FIFO 1 Message Lost Enable
6 RF1FE R/W 0h Rx FIFO 1 Full Enable
5 RF1WE R/W 0h Rx FIFO 1 Watermark Reached Enable
4 RF1NE R/W 0h Rx FIFO 1 New Message Enable
3 RF0LE R/W 0h Rx FIFO 0 Message Lost Enable
2 RF0FE R/W 0h Rx FIFO 0 Full Enable
1 RF0WE R/W 0h Rx FIFO 0 Watermark Reached Enable
0 RF0NE R/W 0h Rx FIFO 0 New Message Enable

21.25 MCAN_ILS (Offset = 7058h) [Reset = 00000000h]

MCAN_ILS is shown in Figure 21-25 and described in Table 21-27.

Return to the Summary Table.

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.

Figure 21-25 MCAN_ILS
31 30 29 28 27 26 25 24
RESERVED ARAL PEDL PEAL WDIL BOL EWL
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
EPL ELOL BEUL BECL DRXL TOOL MRAFL TSWL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TEFLL TEFFL TEFWL TEFNL TFEL TCFL TCL HPML
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RF1LL RF1FL RF1WL RF1NL RF0LL RF0FL RF0WL RF0NL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 21-27 MCAN_ILS Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29 ARAL R/W 0h Access to Reserved Address Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
28 PEDL R/W 0h Protocol Error in Data Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
27 PEAL R/W 0h Protocol Error in Arbitration Phase Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
26 WDIL R/W 0h Watchdog Interrupt Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
25 BOL R/W 0h Bus_Off Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
24 EWL R/W 0h Warning Status Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
23 EPL R/W 0h Error Passive Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
22 ELOL R/W 0h Error Logging Overflow Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
21 BEUL R/W 0h Bit Error Uncorrected Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
20 BECL R/W 0h Bit Error Corrected Line

A separate interrupt line reserved for corrected bit errors is provided via the MCAN_ERROR_REGS. It advised for the user to use these registers and leave the MCAN_IE.BECE bit cleared to '0' (disabled), thereby relegating this bit to not applicable.
19 DRXL R/W 0h Message Stored to Dedicated Rx Buffer Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
18 TOOL R/W 0h Timeout Occurred Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
17 MRAFL R/W 0h Message RAM Access Failure Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
16 TSWL R/W 0h Timestamp Wraparound Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
15 TEFLL R/W 0h Tx Event FIFO Element Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
14 TEFFL R/W 0h Tx Event FIFO Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
13 TEFWL R/W 0h Tx Event FIFO Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
12 TEFNL R/W 0h Tx Event FIFO New Entry Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
11 TFEL R/W 0h Tx FIFO Empty Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
10 TCFL R/W 0h Transmission Cancellation Finished Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
9 TCL R/W 0h Transmission Completed Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
8 HPML R/W 0h High Priority Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
7 RF1LL R/W 0h Rx FIFO 1 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
6 RF1FL R/W 0h Rx FIFO 1 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
5 RF1WL R/W 0h Rx FIFO 1 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
4 RF1NL R/W 0h Rx FIFO 1 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
3 RF0LL R/W 0h Rx FIFO 0 Message Lost Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
2 RF0FL R/W 0h Rx FIFO 0 Full Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
1 RF0WL R/W 0h Rx FIFO 0 Watermark Reached Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1
0 RF0NL R/W 0h Rx FIFO 0 New Message Line
0 Interrupt source is assigned to Interrupt Line 0
1 Interrupt source is assigned to Interrupt Line 1

21.26 MCAN_ILE (Offset = 705Ch) [Reset = 00000000h]

MCAN_ILE is shown in Figure 21-26 and described in Table 21-28.

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MCAN Interrupt Line Enable

Figure 21-26 MCAN_ILE
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EINT1 EINT0
R-0h R/W-0h R/W-0h
Table 21-28 MCAN_ILE Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 EINT1 R/W 0h Enable Interrupt Line 1
0 Interrupt Line 1 is disabled
1 Interrupt Line 1 is enabled
0 EINT0 R/W 0h Enable Interrupt Line 0
0 Interrupt Line 0 is disabled
1 Interrupt Line 0 is enabled

21.27 MCAN_GFC (Offset = 7080h) [Reset = 00000000h]

MCAN_GFC is shown in Figure 21-27 and described in Table 21-29.

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MCAN Global Filter Configuration

Figure 21-27 MCAN_GFC
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ANFS ANFE RRFS RRFE
R-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
Table 21-29 MCAN_GFC Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-4 ANFS R/WQ 0h Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3-2 ANFE R/WQ 0h Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.
00 Accept in Rx FIFO 0
01 Accept in Rx FIFO 1
10 Reject
11 Reject

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1 RRFS R/WQ 0h Reject Remote Frames Standard
0 Filter remote frames with 11-bit standard IDs
1 Reject all remote frames with 11-bit standard IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
0 RRFE R/WQ 0h Reject Remote Frames Extended
0 Filter remote frames with 29-bit extended IDs
1 Reject all remote frames with 29-bit extended IDs

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.28 MCAN_SIDFC (Offset = 7084h) [Reset = 00000000h]

MCAN_SIDFC is shown in Figure 21-28 and described in Table 21-30.

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MCAN Standard ID Filter Configuration

Figure 21-28 MCAN_SIDFC
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
LSS
R/WQ-0h
15 14 13 12 11 10 9 8
FLSSA
R/WQ-0h
7 6 5 4 3 2 1 0
FLSSA RESERVED
R/WQ-0h R-0h
Table 21-30 MCAN_SIDFC Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-16 LSS R/WQ 0h List Size Standard
0 No standard Message ID filter
1-128 Number of standard Message ID filter elements
>128 Values greater than 128 are interpreted as 128
15-2 FLSSA R/WQ 0h Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address).
1-0 RESERVED R 0h

21.29 MCAN_XIDFC (Offset = 7088h) [Reset = 00000000h]

MCAN_XIDFC is shown in Figure 21-29 and described in Table 21-31.

Return to the Summary Table.

MCAN Extended ID Filter Configuration

Figure 21-29 MCAN_XIDFC
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED LSE
R-0h R/WQ-0h
15 14 13 12 11 10 9 8
FLESA
R/WQ-0h
7 6 5 4 3 2 1 0
FLESA RESERVED
R/WQ-0h R-0h
Table 21-31 MCAN_XIDFC Field Descriptions
Bit Field Type Reset Description
31-23 RESERVED R 0h
22-16 LSE R/WQ 0h Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2 FLESA R/WQ 0h List Size Extended
0 No extended Message ID filter
1-64 Number of extended Message ID filter elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0 RESERVED R 0h

21.30 MCAN_XIDAM (Offset = 7090h) [Reset = 1FFFFFFFh]

MCAN_XIDAM is shown in Figure 21-30 and described in Table 21-32.

Return to the Summary Table.

MCAN Extended ID and Mask

Figure 21-30 MCAN_XIDAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EIDM
R-0h R/WQ-1FFFFFFFh
Table 21-32 MCAN_XIDAM Field Descriptions
Bit Field Type Reset Description
31-29 RESERVED R 0h
28-0 EIDM R/WQ 1FFFFFFFh Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.31 MCAN_HPMS (Offset = 7094h) [Reset = 00000000h]

MCAN_HPMS is shown in Figure 21-31 and described in Table 21-33.

Return to the Summary Table.

This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Figure 21-31 MCAN_HPMS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
FLST FIDX
R-0h R-0h
7 6 5 4 3 2 1 0
MSI BIDX
R-0h R-0h
Table 21-33 MCAN_HPMS Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15 FLST R 0h Filter List. Indicates the filter list of the matching filter element.
0 Standard Filter List
1 Extended Filter List
14-8 FIDX R 0h Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.
7-6 MSI R 0h Message Storage Indicator
00 No FIFO selected
01 FIFO message lost
10 Message stored in FIFO 0
11 Message stored in FIFO 1
5-0 BIDX R 0h Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'.

21.32 MCAN_NDAT1 (Offset = 7098h) [Reset = 00000000h]

MCAN_NDAT1 is shown in Figure 21-32 and described in Table 21-34.

Return to the Summary Table.

MCAN New Data 1

Figure 21-32 MCAN_NDAT1
31 30 29 28 27 26 25 24
ND31 ND30 ND29 ND28 ND27 ND26 ND25 ND24
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
23 22 21 20 19 18 17 16
ND23 ND22 ND21 ND20 ND19 ND18 ND17 ND16
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
15 14 13 12 11 10 9 8
ND15 ND14 ND13 ND12 ND11 ND10 ND9 ND8
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
Table 21-34 MCAN_NDAT1 Field Descriptions
Bit Field Type Reset Description
31 ND31 R/W1C 0h New Data RX Buffer 31
0 Rx Buffer not updated
1 Rx Buffer updated from new message
30 ND30 R/W1C 0h New Data RX Buffer 30
0 Rx Buffer not updated
1 Rx Buffer updated from new message
29 ND29 R/W1C 0h New Data RX Buffer 29
0 Rx Buffer not updated
1 Rx Buffer updated from new message
28 ND28 R/W1C 0h New Data RX Buffer 28
0 Rx Buffer not updated
1 Rx Buffer updated from new message
27 ND27 R/W1C 0h New Data RX Buffer 27
0 Rx Buffer not updated
1 Rx Buffer updated from new message
26 ND26 R/W1C 0h New Data RX Buffer 26
0 Rx Buffer not updated
1 Rx Buffer updated from new message
25 ND25 R/W1C 0h New Data RX Buffer 25
0 Rx Buffer not updated
1 Rx Buffer updated from new message
24 ND24 R/W1C 0h New Data RX Buffer 24
0 Rx Buffer not updated
1 Rx Buffer updated from new message
23 ND23 R/W1C 0h New Data RX Buffer 23
0 Rx Buffer not updated
1 Rx Buffer updated from new message
22 ND22 R/W1C 0h New Data RX Buffer 22
0 Rx Buffer not updated
1 Rx Buffer updated from new message
21 ND21 R/W1C 0h New Data RX Buffer 21
0 Rx Buffer not updated
1 Rx Buffer updated from new message
20 ND20 R/W1C 0h New Data RX Buffer 20
0 Rx Buffer not updated
1 Rx Buffer updated from new message
19 ND19 R/W1C 0h New Data RX Buffer 19
0 Rx Buffer not updated
1 Rx Buffer updated from new message
18 ND18 R/W1C 0h New Data RX Buffer 18
0 Rx Buffer not updated
1 Rx Buffer updated from new message
17 ND17 R/W1C 0h New Data RX Buffer 17
0 Rx Buffer not updated
1 Rx Buffer updated from new message
16 ND16 R/W1C 0h New Data RX Buffer 16
0 Rx Buffer not updated
1 Rx Buffer updated from new message
15 ND15 R/W1C 0h New Data RX Buffer 15
0 Rx Buffer not updated
1 Rx Buffer updated from new message
14 ND14 R/W1C 0h New Data RX Buffer 14
0 Rx Buffer not updated
1 Rx Buffer updated from new message
13 ND13 R/W1C 0h New Data RX Buffer 13
0 Rx Buffer not updated
1 Rx Buffer updated from new message
12 ND12 R/W1C 0h New Data RX Buffer 12
0 Rx Buffer not updated
1 Rx Buffer updated from new message
11 ND11 R/W1C 0h New Data RX Buffer 11
0 Rx Buffer not updated
1 Rx Buffer updated from new message
10 ND10 R/W1C 0h New Data RX Buffer 10
0 Rx Buffer not updated
1 Rx Buffer updated from new message
9 ND9 R/W1C 0h New Data RX Buffer 9
0 Rx Buffer not updated
1 Rx Buffer updated from new message
8 ND8 R/W1C 0h New Data RX Buffer 8
0 Rx Buffer not updated
1 Rx Buffer updated from new message
7 ND7 R/W1C 0h New Data RX Buffer 7
0 Rx Buffer not updated
1 Rx Buffer updated from new message
6 ND6 R/W1C 0h New Data RX Buffer 6
0 Rx Buffer not updated
1 Rx Buffer updated from new message
5 ND5 R/W1C 0h New Data RX Buffer 5
0 Rx Buffer not updated
1 Rx Buffer updated from new message
4 ND4 R/W1C 0h New Data RX Buffer 4
0 Rx Buffer not updated
1 Rx Buffer updated from new message
3 ND3 R/W1C 0h New Data RX Buffer 3
0 Rx Buffer not updated
1 Rx Buffer updated from new message
2 ND2 R/W1C 0h New Data RX Buffer 2
0 Rx Buffer not updated
1 Rx Buffer updated from new message
1 ND1 R/W1C 0h New Data RX Buffer 1
0 Rx Buffer not updated
1 Rx Buffer updated from new message
0 ND0 R/W1C 0h New Data RX Buffer 0
0 Rx Buffer not updated
1 Rx Buffer updated from new message

21.33 MCAN_NDAT2 (Offset = 709Ch) [Reset = 00000000h]

MCAN_NDAT2 is shown in Figure 21-33 and described in Table 21-35.

Return to the Summary Table.

MCAN New Data 2

Figure 21-33 MCAN_NDAT2
31 30 29 28 27 26 25 24
ND63 ND62 ND61 ND60 ND59 ND58 ND57 ND56
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
23 22 21 20 19 18 17 16
ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
15 14 13 12 11 10 9 8
ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
Table 21-35 MCAN_NDAT2 Field Descriptions
Bit Field Type Reset Description
31 ND63 R/W1C 0h New Data RX Buffer 63
0 Rx Buffer not updated
1 Rx Buffer updated from new message
30 ND62 R/W1C 0h New Data RX Buffer 62
0 Rx Buffer not updated
1 Rx Buffer updated from new message
29 ND61 R/W1C 0h New Data RX Buffer 61
0 Rx Buffer not updated
1 Rx Buffer updated from new message
28 ND60 R/W1C 0h New Data RX Buffer 60
0 Rx Buffer not updated
1 Rx Buffer updated from new message
27 ND59 R/W1C 0h New Data RX Buffer 59
0 Rx Buffer not updated
1 Rx Buffer updated from new message
26 ND58 R/W1C 0h New Data RX Buffer 58
0 Rx Buffer not updated
1 Rx Buffer updated from new message
25 ND57 R/W1C 0h New Data RX Buffer 57
0 Rx Buffer not updated
1 Rx Buffer updated from new message
24 ND56 R/W1C 0h New Data RX Buffer 56
0 Rx Buffer not updated
1 Rx Buffer updated from new message
23 ND55 R/W1C 0h New Data RX Buffer 55
0 Rx Buffer not updated
1 Rx Buffer updated from new message
22 ND54 R/W1C 0h New Data RX Buffer 54
0 Rx Buffer not updated
1 Rx Buffer updated from new message
21 ND53 R/W1C 0h New Data RX Buffer 53
0 Rx Buffer not updated
1 Rx Buffer updated from new message
20 ND52 R/W1C 0h New Data RX Buffer 52
0 Rx Buffer not updated
1 Rx Buffer updated from new message
19 ND51 R/W1C 0h New Data RX Buffer 51
0 Rx Buffer not updated
1 Rx Buffer updated from new message
18 ND50 R/W1C 0h New Data RX Buffer 50
0 Rx Buffer not updated
1 Rx Buffer updated from new message
17 ND49 R/W1C 0h New Data RX Buffer 49
0 Rx Buffer not updated
1 Rx Buffer updated from new message
16 ND48 R/W1C 0h New Data RX Buffer 48
0 Rx Buffer not updated
1 Rx Buffer updated from new message
15 ND47 R/W1C 0h New Data RX Buffer 47
0 Rx Buffer not updated
1 Rx Buffer updated from new message
14 ND46 R/W1C 0h New Data RX Buffer 46
0 Rx Buffer not updated
1 Rx Buffer updated from new message
13 ND45 R/W1C 0h New Data RX Buffer 45
0 Rx Buffer not updated
1 Rx Buffer updated from new message
12 ND44 R/W1C 0h New Data RX Buffer 44
0 Rx Buffer not updated
1 Rx Buffer updated from new message
11 ND43 R/W1C 0h New Data RX Buffer 43
0 Rx Buffer not updated
1 Rx Buffer updated from new message
10 ND42 R/W1C 0h New Data RX Buffer 42
0 Rx Buffer not updated
1 Rx Buffer updated from new message
9 ND41 R/W1C 0h New Data RX Buffer 41
0 Rx Buffer not updated
1 Rx Buffer updated from new message
8 ND40 R/W1C 0h New Data RX Buffer 40
0 Rx Buffer not updated
1 Rx Buffer updated from new message
7 ND39 R/W1C 0h New Data RX Buffer 39
0 Rx Buffer not updated
1 Rx Buffer updated from new message
6 ND38 R/W1C 0h New Data RX Buffer 38
0 Rx Buffer not updated
1 Rx Buffer updated from new message
5 ND37 R/W1C 0h New Data RX Buffer 37
0 Rx Buffer not updated
1 Rx Buffer updated from new message
4 ND36 R/W1C 0h New Data RX Buffer 36
0 Rx Buffer not updated
1 Rx Buffer updated from new message
3 ND35 R/W1C 0h New Data RX Buffer 35
0 Rx Buffer not updated
1 Rx Buffer updated from new message
2 ND34 R/W1C 0h New Data RX Buffer 34
0 Rx Buffer not updated
1 Rx Buffer updated from new message
1 ND33 R/W1C 0h New Data RX Buffer 33
0 Rx Buffer not updated
1 Rx Buffer updated from new message
0 ND32 R/W1C 0h New Data RX Buffer 32
0 Rx Buffer not updated
1 Rx Buffer updated from new message

21.34 MCAN_RXF0C (Offset = 70A0h) [Reset = 00000000h]

MCAN_RXF0C is shown in Figure 21-34 and described in Table 21-36.

Return to the Summary Table.

MCAN Rx FIFO 0 Configuration

Figure 21-34 MCAN_RXF0C
31 30 29 28 27 26 25 24
F0OM F0WM
R/WQ-0h R/WQ-0h
23 22 21 20 19 18 17 16
RESERVED F0S
R-0h R/WQ-0h
15 14 13 12 11 10 9 8
F0SA
R/WQ-0h
7 6 5 4 3 2 1 0
F0SA RESERVED
R/WQ-0h R-0h
Table 21-36 MCAN_RXF0C Field Descriptions
Bit Field Type Reset Description
31 F0OM R/WQ 0h FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode.
0 FIFO 0 blocking mode
1 FIFO 0 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24 F0WM R/WQ 0h Rx FIFO 0 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23 RESERVED R 0h
22-16 F0S R/WQ 0h Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1.
0 No Rx FIFO 0
1-64 Number of Rx FIFO 0 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2 F0SA R/WQ 0h Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0 RESERVED R 0h

21.35 MCAN_RXF0S (Offset = 70A4h) [Reset = 00000000h]

MCAN_RXF0S is shown in Figure 21-35 and described in Table 21-37.

Return to the Summary Table.

MCAN Rx FIFO 0 Status

Figure 21-35 MCAN_RXF0S
31 30 29 28 27 26 25 24
RESERVED RF0L F0F
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED F0PI
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED F0GI
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED F0FL
R-0h R-0h
Table 21-37 MCAN_RXF0S Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R 0h
25 RF0L R 0h Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag.
24 F0F R 0h Rx FIFO 0 Full
0 Rx FIFO 0 not full
1 Rx FIFO 0 full
23-22 RESERVED R 0h
21-16 F0PI R 0h Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63.
15-14 RESERVED R 0h
13-8 F0GI R 0h Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63.
7 RESERVED R 0h
6-0 F0FL R 0h Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64.

21.36 MCAN_RXF0A (Offset = 70A8h) [Reset = 00000000h]

MCAN_RXF0A is shown in Figure 21-36 and described in Table 21-38.

Return to the Summary Table.

MCAN Rx FIFO 0 Acknowledge

Figure 21-36 MCAN_RXF0A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED F0AI
R-0h R/W-0h
Table 21-38 MCAN_RXF0A Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-0 F0AI R/W 0h Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.

21.37 MCAN_RXBC (Offset = 70ACh) [Reset = 00000000h]

MCAN_RXBC is shown in Figure 21-37 and described in Table 21-39.

Return to the Summary Table.

MCAN Rx Buffer Configuration

Figure 21-37 MCAN_RXBC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RBSA RESERVED
R-0h R/WQ-0h R-0h
Table 21-39 MCAN_RXBC Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-2 RBSA R/WQ 0h Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).

+I466
1-0 RESERVED R 0h

21.38 MCAN_RXF1C (Offset = 70B0h) [Reset = 00000000h]

MCAN_RXF1C is shown in Figure 21-38 and described in Table 21-40.

Return to the Summary Table.

MCAN Rx FIFO 1 Configuration

Figure 21-38 MCAN_RXF1C
31 30 29 28 27 26 25 24
F1OM F1WM
R/WQ-0h R/WQ-0h
23 22 21 20 19 18 17 16
RESERVED F1S
R-0h R/WQ-0h
15 14 13 12 11 10 9 8
F1SA
R/WQ-0h
7 6 5 4 3 2 1 0
F1SA RESERVED
R/WQ-0h R-0h
Table 21-40 MCAN_RXF1C Field Descriptions
Bit Field Type Reset Description
31 F1OM R/WQ 0h FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode.
0 FIFO 1 blocking mode
1 FIFO 1 overwrite mode

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
30-24 F1WM R/WQ 0h Rx FIFO 1 Watermark
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64 Watermark interrupt disabled

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23 RESERVED R 0h
22-16 F1S R/WQ 0h Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1.
0 No Rx FIFO 1
1-64 Number of Rx FIFO 1 elements
>64 Values greater than 64 are interpreted as 64

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2 F1SA R/WQ 0h Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address).
1-0 RESERVED R 0h

21.39 MCAN_RXF1S (Offset = 70B4h) [Reset = 00000000h]

MCAN_RXF1S is shown in Figure 21-39 and described in Table 21-41.

Return to the Summary Table.

MCAN Rx FIFO 1 Status

Figure 21-39 MCAN_RXF1S
31 30 29 28 27 26 25 24
DMS RESERVED RF1L F1F
R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED F1PI
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED F1GI
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED F1FL
R-0h R-0h
Table 21-41 MCAN_RXF1S Field Descriptions
Bit Field Type Reset Description
31-30 DMS R 0h Debug Message Status
00 Idle state, wait for reception of debug messages
01 Debug message A received
10 Debug messages A, B received
11 Debug messages A, B, C received
29-26 RESERVED R 0h
25 RF1L R 0h Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
0 No Rx FIFO 1 message lost
1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag.
24 F1F R 0h Rx FIFO 1 Full
0 Rx FIFO 1 not full
1 Rx FIFO 1 full
23-22 RESERVED R 0h
21-16 F1PI R 0h Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63.
15-14 RESERVED R 0h
13-8 F1GI R 0h Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63.
7 RESERVED R 0h
6-0 F1FL R 0h Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64.

21.40 MCAN_RXF1A (Offset = 70B8h) [Reset = 00000000h]

MCAN_RXF1A is shown in Figure 21-40 and described in Table 21-42.

Return to the Summary Table.

MCAN Rx FIFO 1 Acknowledge

Figure 21-40 MCAN_RXF1A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED F1AI
R-0h R/W-0h
Table 21-42 MCAN_RXF1A Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-0 F1AI R/W 0h Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.

21.41 MCAN_RXESC (Offset = 70BCh) [Reset = 00000000h]

MCAN_RXESC is shown in Figure 21-41 and described in Table 21-43.

Return to the Summary Table.

Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.

Figure 21-41 MCAN_RXESC
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RBDS
R-0h R/WQ-0h
7 6 5 4 3 2 1 0
RESERVED F1DS RESERVED F0DS
R-0h R/WQ-0h R-0h R/WQ-0h
Table 21-43 MCAN_RXESC Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10-8 RBDS R/WQ 0h Rx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
7 RESERVED R 0h
6-4 F1DS R/WQ 0h Rx FIFO 1 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
3 RESERVED R 0h
2-0 F0DS R/WQ 0h Rx FIFO 0 Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.42 MCAN_TXBC (Offset = 70C0h) [Reset = 00000000h]

MCAN_TXBC is shown in Figure 21-42 and described in Table 21-44.

Return to the Summary Table.

MCAN Tx Buffer Configuration

Figure 21-42 MCAN_TXBC
31 30 29 28 27 26 25 24
RESERVED TFQM TFQS
R-0h R/WQ-0h R/WQ-0h
23 22 21 20 19 18 17 16
RESERVED NDTB
R-0h R/WQ-0h
15 14 13 12 11 10 9 8
TBSA
R/WQ-0h
7 6 5 4 3 2 1 0
TBSA RESERVED
R/WQ-0h R-0h
Table 21-44 MCAN_TXBC Field Descriptions
Bit Field Type Reset Description
31 RESERVED R 0h
30 TFQM R/WQ 0h Tx FIFO/Queue Mode
0 Tx FIFO operation
1 Tx Queue operation

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
29-24 TFQS R/WQ 0h Transmit FIFO/Queue Size
0 No Tx FIFO/Queue
1-32 Number of Tx Buffers used for Tx FIFO/Queue
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
23-22 RESERVED R 0h
21-16 NDTB R/WQ 0h Number of Dedicated Transmit Buffers
0 No Dedicated Tx Buffers
1-32 Number of Dedicated Tx Buffers
>32 Values greater than 32 are interpreted as 32

Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check
for erroneous configurations. The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
15-2 TBSA R/WQ 0h Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.
1-0 RESERVED R 0h

21.43 MCAN_TXFQS (Offset = 70C4h) [Reset = 00000000h]

MCAN_TXFQS is shown in Figure 21-43 and described in Table 21-45.

Return to the Summary Table.

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).

Figure 21-43 MCAN_TXFQS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED TFQF TFQP
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED TFGI
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TFFL
R-0h R-0h
Table 21-45 MCAN_TXFQS Field Descriptions
Bit Field Type Reset Description
31-22 RESERVED R 0h
21 TFQF R 0h Tx FIFO/Queue Full
0 Tx FIFO/Queue not full
1 Tx FIFO/Queue full
20-16 TFQP R 0h Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31.

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
15-13 RESERVED R 0h
12-8 TFGI R 0h Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO.
7-6 RESERVED R 0h
5-0 TFFL R 0h Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1').

21.44 MCAN_TXESC (Offset = 70C8h) [Reset = 00000000h]

MCAN_TXESC is shown in Figure 21-44 and described in Table 21-46.

Return to the Summary Table.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Figure 21-44 MCAN_TXESC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TBDS
R-0h R/WQ-0h
Table 21-46 MCAN_TXESC Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h
2-0 TBDS R/WQ 0h Tx Buffer Data Field Size
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
101 32 byte data field
110 48 byte data field
111 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as '0xCC' (padding bytes).

Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'.

21.45 MCAN_TXBRP (Offset = 70CCh) [Reset = 00000000h]

MCAN_TXBRP is shown in Figure 21-45 and described in Table 21-47.

Return to the Summary Table.

MCAN Tx Buffer Request Pending

Figure 21-45 MCAN_TXBRP
31 30 29 28 27 26 25 24
TRP31 TRP30 TRP29 TRP28 TRP27 TRP26 TRP25 TRP24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
TRP23 TRP22 TRP21 TRP20 TRP19 TRP18 TRP17 TRP16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
TRP15 TRP14 TRP13 TRP12 TRP11 TRP10 TRP9 TRP8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
TRP7 TRP6 TRP5 TRP4 TRP3 TRP2 TRP1 TRP0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 21-47 MCAN_TXBRP Field Descriptions
Bit Field Type Reset Description
31 TRP31 R 0h Transmission Request Pending 31. See description for bit 0.
30 TRP30 R 0h Transmission Request Pending 30. See description for bit 0.
29 TRP29 R 0h Transmission Request Pending 29. See description for bit 0.
28 TRP28 R 0h Transmission Request Pending 28. See description for bit 0.
27 TRP27 R 0h Transmission Request Pending 27. See description for bit 0.
26 TRP26 R 0h Transmission Request Pending 26. See description for bit 0.
25 TRP25 R 0h Transmission Request Pending 25. See description for bit 0.
24 TRP24 R 0h Transmission Request Pending 24. See description for bit 0.
23 TRP23 R 0h Transmission Request Pending 23. See description for bit 0.
22 TRP22 R 0h Transmission Request Pending 22. See description for bit 0.
21 TRP21 R 0h Transmission Request Pending 21. See description for bit 0.
20 TRP20 R 0h Transmission Request Pending 20. See description for bit 0.
19 TRP19 R 0h Transmission Request Pending 19. See description for bit 0.
18 TRP18 R 0h Transmission Request Pending 18. See description for bit 0.
17 TRP17 R 0h Transmission Request Pending 17. See description for bit 0.
16 TRP16 R 0h Transmission Request Pending 16. See description for bit 0.
15 TRP15 R 0h Transmission Request Pending 15. See description for bit 0.
14 TRP14 R 0h Transmission Request Pending 14. See description for bit 0.
13 TRP13 R 0h Transmission Request Pending 13. See description for bit 0.
12 TRP12 R 0h Transmission Request Pending 12. See description for bit 0.
11 TRP11 R 0h Transmission Request Pending 11. See description for bit 0.
10 TRP10 R 0h Transmission Request Pending 10. See description for bit 0.
9 TRP9 R 0h Transmission Request Pending 9. See description for bit 0.
8 TRP8 R 0h Transmission Request Pending 8. See description for bit 0.
7 TRP7 R 0h Transmission Request Pending 7. See description for bit 0.
6 TRP6 R 0h Transmission Request Pending 6. See description for bit 0.
5 TRP5 R 0h Transmission Request Pending 5. See description for bit 0.
4 TRP4 R 0h Transmission Request Pending 4. See description for bit 0.
3 TRP3 R 0h Transmission Request Pending 3. See description for bit 0.
2 TRP2 R 0h Transmission Request Pending 2. See description for bit 0.
1 TRP1 R 0h Transmission Request Pending 1. See description for bit 0.
0 TRP0 R 0h Transmission Request Pending 0.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR.

TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via TXBCF
- after successful transmission together with the corresponding TXBTO bit
- when the transmission has not yet been started at the point of cancellation
- when the transmission has been aborted due to lost arbitration
- when an error occurred during frame transmission

In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions.
0 No transmission request pending
1 Transmission request pending

Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset.

21.46 MCAN_TXBAR (Offset = 70D0h) [Reset = 00000000h]

MCAN_TXBAR is shown in Figure 21-46 and described in Table 21-48.

Return to the Summary Table.

MCAN Tx Buffer Add Request

Figure 21-46 MCAN_TXBAR
31 30 29 28 27 26 25 24
AR31 AR30 AR29 AR28 AR27 AR26 AR25 AR24
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
23 22 21 20 19 18 17 16
AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
15 14 13 12 11 10 9 8
AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
7 6 5 4 3 2 1 0
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
Table 21-48 MCAN_TXBAR Field Descriptions
Bit Field Type Reset Description
31 AR31 R/WQ 0h Add Request 31. See description for bit 0.
30 AR30 R/WQ 0h Add Request 30. See description for bit 0.
29 AR29 R/WQ 0h Add Request 29. See description for bit 0.
28 AR28 R/WQ 0h Add Request 28. See description for bit 0.
27 AR27 R/WQ 0h Add Request 27. See description for bit 0.
26 AR26 R/WQ 0h Add Request 26. See description for bit 0.
25 AR25 R/WQ 0h Add Request 25. See description for bit 0.
24 AR24 R/WQ 0h Add Request 24. See description for bit 0.
23 AR23 R/WQ 0h Add Request 23. See description for bit 0.
22 AR22 R/WQ 0h Add Request 22. See description for bit 0.
21 AR21 R/WQ 0h Add Request 21. See description for bit 0.
20 AR20 R/WQ 0h Add Request 20. See description for bit 0.
19 AR19 R/WQ 0h Add Request 19. See description for bit 0.
18 AR18 R/WQ 0h Add Request 18. See description for bit 0.
17 AR17 R/WQ 0h Add Request 17. See description for bit 0.
16 AR16 R/WQ 0h Add Request 16. See description for bit 0.
15 AR15 R/WQ 0h Add Request 15. See description for bit 0.
14 AR14 R/WQ 0h Add Request 14. See description for bit 0.
13 AR13 R/WQ 0h Add Request 13. See description for bit 0.
12 AR12 R/WQ 0h Add Request 12. See description for bit 0.
11 AR11 R/WQ 0h Add Request 11. See description for bit 0.
10 AR10 R/WQ 0h Add Request 10. See description for bit 0.
9 AR9 R/WQ 0h Add Request 9. See description for bit 0.
8 AR8 R/WQ 0h Add Request 8. See description for bit 0.
7 AR7 R/WQ 0h Add Request 7. See description for bit 0.
6 AR6 R/WQ 0h Add Request 6. See description for bit 0.
5 AR5 R/WQ 0h Add Request 5. See description for bit 0.
4 AR4 R/WQ 0h Add Request 4. See description for bit 0.
3 AR3 R/WQ 0h Add Request 3. See description for bit 0.
2 AR2 R/WQ 0h Add Request 2. See description for bit 0.
1 AR1 R/WQ 0h Add Request 1. See description for bit 0.
0 AR0 R/WQ 0h Add Request 0.

Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.
0 No transmission request added
1 Transmission requested added

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored.

Qualified Write is possible only with CCCR.CCE='0'

21.47 MCAN_TXBCR (Offset = 70D4h) [Reset = 00000000h]

MCAN_TXBCR is shown in Figure 21-47 and described in Table 21-49.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Request

Figure 21-47 MCAN_TXBCR
31 30 29 28 27 26 25 24
CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
23 22 21 20 19 18 17 16
CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
15 14 13 12 11 10 9 8
CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
7 6 5 4 3 2 1 0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h R/WQ-0h
Table 21-49 MCAN_TXBCR Field Descriptions
Bit Field Type Reset Description
31 CR31 R/WQ 0h Cancellation Request 31. See description for bit 0.
30 CR30 R/WQ 0h Cancellation Request 30. See description for bit 0.
29 CR29 R/WQ 0h Cancellation Request 29. See description for bit 0.
28 CR28 R/WQ 0h Cancellation Request 28. See description for bit 0.
27 CR27 R/WQ 0h Cancellation Request 27. See description for bit 0.
26 CR26 R/WQ 0h Cancellation Request 26. See description for bit 0.
25 CR25 R/WQ 0h Cancellation Request 25. See description for bit 0.
24 CR24 R/WQ 0h Cancellation Request 24. See description for bit 0.
23 CR23 R/WQ 0h Cancellation Request 23. See description for bit 0.
22 CR22 R/WQ 0h Cancellation Request 22. See description for bit 0.
21 CR21 R/WQ 0h Cancellation Request 21. See description for bit 0.
20 CR20 R/WQ 0h Cancellation Request 20. See description for bit 0.
19 CR19 R/WQ 0h Cancellation Request 19. See description for bit 0.
18 CR18 R/WQ 0h Cancellation Request 18. See description for bit 0.
17 CR17 R/WQ 0h Cancellation Request 17. See description for bit 0.
16 CR16 R/WQ 0h Cancellation Request 16. See description for bit 0.
15 CR15 R/WQ 0h Cancellation Request 15. See description for bit 0.
14 CR14 R/WQ 0h Cancellation Request 14. See description for bit 0.
13 CR13 R/WQ 0h Cancellation Request 13. See description for bit 0.
12 CR12 R/WQ 0h Cancellation Request 12. See description for bit 0.
11 CR11 R/WQ 0h Cancellation Request 11. See description for bit 0.
10 CR10 R/WQ 0h Cancellation Request 10. See description for bit 0.
9 CR9 R/WQ 0h Cancellation Request 9. See description for bit 0.
8 CR8 R/WQ 0h Cancellation Request 8. See description for bit 0.
7 CR7 R/WQ 0h Cancellation Request 7. See description for bit 0.
6 CR6 R/WQ 0h Cancellation Request 6. See description for bit 0.
5 CR5 R/WQ 0h Cancellation Request 5. See description for bit 0.
4 CR4 R/WQ 0h Cancellation Request 4. See description for bit 0.
3 CR3 R/WQ 0h Cancellation Request 3. See description for bit 0.
2 CR2 R/WQ 0h Cancellation Request 2. See description for bit 0.
1 CR1 R/WQ 0h Cancellation Request 1. See description for bit 0.
0 CR0 R/WQ 0h Cancellation Request 0.

Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
0 No cancellation pending
1 Cancellation pending

Qualified Write is possible only with CCCR.CCE='0'

21.48 MCAN_TXBTO (Offset = 70D8h) [Reset = 00000000h]

MCAN_TXBTO is shown in Figure 21-48 and described in Table 21-50.

Return to the Summary Table.

MCAN Tx Buffer Transmission Occurred

Figure 21-48 MCAN_TXBTO
31 30 29 28 27 26 25 24
TO31 TO30 TO29 TO28 TO27 TO26 TO25 TO24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
TO23 TO22 TO21 TO20 TO19 TO18 TO17 TO16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
TO15 TO14 TO13 TO12 TO11 TO10 TO9 TO8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 21-50 MCAN_TXBTO Field Descriptions
Bit Field Type Reset Description
31 TO31 R 0h Transmission Occurred 31. See description for bit 0.
30 TO30 R 0h Transmission Occurred 30. See description for bit 0.
29 TO29 R 0h Transmission Occurred 29. See description for bit 0.
28 TO28 R 0h Transmission Occurred 28. See description for bit 0.
27 TO27 R 0h Transmission Occurred 27. See description for bit 0.
26 TO26 R 0h Transmission Occurred 26. See description for bit 0.
25 TO25 R 0h Transmission Occurred 25. See description for bit 0.
24 TO24 R 0h Transmission Occurred 24. See description for bit 0.
23 TO23 R 0h Transmission Occurred 23. See description for bit 0.
22 TO22 R 0h Transmission Occurred 22. See description for bit 0.
21 TO21 R 0h Transmission Occurred 21. See description for bit 0.
20 TO20 R 0h Transmission Occurred 20. See description for bit 0.
19 TO19 R 0h Transmission Occurred 19. See description for bit 0.
18 TO18 R 0h Transmission Occurred 18. See description for bit 0.
17 TO17 R 0h Transmission Occurred 17. See description for bit 0.
16 TO16 R 0h Transmission Occurred 16. See description for bit 0.
15 TO15 R 0h Transmission Occurred 15. See description for bit 0.
14 TO14 R 0h Transmission Occurred 14. See description for bit 0.
13 TO13 R 0h Transmission Occurred 13. See description for bit 0.
12 TO12 R 0h Transmission Occurred 12. See description for bit 0.
11 TO11 R 0h Transmission Occurred 11. See description for bit 0.
10 TO10 R 0h Transmission Occurred 10. See description for bit 0.
9 TO9 R 0h Transmission Occurred 9. See description for bit 0.
8 TO8 R 0h Transmission Occurred 8. See description for bit 0.
7 TO7 R 0h Transmission Occurred 7. See description for bit 0.
6 TO6 R 0h Transmission Occurred 6. See description for bit 0.
5 TO5 R 0h Transmission Occurred 5. See description for bit 0.
4 TO4 R 0h Transmission Occurred 4. See description for bit 0.
3 TO3 R 0h Transmission Occurred 3. See description for bit 0.
2 TO2 R 0h Transmission Occurred 2. See description for bit 0.
1 TO1 R 0h Transmission Occurred 1. See description for bit 0.
0 TO0 R 0h Transmission Occurred 0.

Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmission occurred
1 Transmission occurred

21.49 MCAN_TXBCF (Offset = 70DCh) [Reset = 00000000h]

MCAN_TXBCF is shown in Figure 21-49 and described in Table 21-51.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished

Figure 21-49 MCAN_TXBCF
31 30 29 28 27 26 25 24
CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
23 22 21 20 19 18 17 16
CF23 CF22 CF21 CF20 CF19 CF18 CF17 CF16
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
CF15 CF14 CF13 CF12 CF11 CF10 CF9 CF8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 21-51 MCAN_TXBCF Field Descriptions
Bit Field Type Reset Description
31 CF31 R 0h Cancellation Finished 31. See description for bit 0.
30 CF30 R 0h Cancellation Finished 30. See description for bit 0.
29 CF29 R 0h Cancellation Finished 29. See description for bit 0.
28 CF28 R 0h Cancellation Finished 28. See description for bit 0.
27 CF27 R 0h Cancellation Finished 27. See description for bit 0.
26 CF26 R 0h Cancellation Finished 26. See description for bit 0.
25 CF25 R 0h Cancellation Finished 25. See description for bit 0.
24 CF24 R 0h Cancellation Finished 24. See description for bit 0.
23 CF23 R 0h Cancellation Finished 23. See description for bit 0.
22 CF22 R 0h Cancellation Finished 22. See description for bit 0.
21 CF21 R 0h Cancellation Finished 21. See description for bit 0.
20 CF20 R 0h Cancellation Finished 20. See description for bit 0.
19 CF19 R 0h Cancellation Finished 19. See description for bit 0.
18 CF18 R 0h Cancellation Finished 18. See description for bit 0.
17 CF17 R 0h Cancellation Finished 17. See description for bit 0.
16 CF16 R 0h Cancellation Finished 16. See description for bit 0.
15 CF15 R 0h Cancellation Finished 15. See description for bit 0.
14 CF14 R 0h Cancellation Finished 14. See description for bit 0.
13 CF13 R 0h Cancellation Finished 13. See description for bit 0.
12 CF12 R 0h Cancellation Finished 12. See description for bit 0.
11 CF11 R 0h Cancellation Finished 11. See description for bit 0.
10 CF10 R 0h Cancellation Finished 10. See description for bit 0.
9 CF9 R 0h Cancellation Finished 9. See description for bit 0.
8 CF8 R 0h Cancellation Finished 8. See description for bit 0.
7 CF7 R 0h Cancellation Finished 7. See description for bit 0.
6 CF6 R 0h Cancellation Finished 6. See description for bit 0.
5 CF5 R 0h Cancellation Finished 5. See description for bit 0.
4 CF4 R 0h Cancellation Finished 4. See description for bit 0.
3 CF3 R 0h Cancellation Finished 3. See description for bit 0.
2 CF2 R 0h Cancellation Finished 2. See description for bit 0.
1 CF1 R 0h Cancellation Finished 1. See description for bit 0.
0 CF0 R 0h Cancellation Finished 0.

Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
0 No transmit buffer cancellation
1 Transmit buffer cancellation finished

21.50 MCAN_TXBTIE (Offset = 70E0h) [Reset = 00000000h]

MCAN_TXBTIE is shown in Figure 21-50 and described in Table 21-52.

Return to the Summary Table.

MCAN Tx Buffer Transmission Interrupt Enable

Figure 21-50 MCAN_TXBTIE
31 30 29 28 27 26 25 24
TIE31 TIE30 TIE29 TIE28 TIE27 TIE26 TIE25 TIE24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
TIE23 TIE22 TIE21 TIE20 TIE19 TIE18 TIE17 TIE16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 TIE1 TIE0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 21-52 MCAN_TXBTIE Field Descriptions
Bit Field Type Reset Description
31 TIE31 R/W 0h Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
30 TIE30 R/W 0h Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
29 TIE29 R/W 0h Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
28 TIE28 R/W 0h Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
27 TIE27 R/W 0h Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
26 TIE26 R/W 0h Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
25 TIE25 R/W 0h Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
24 TIE24 R/W 0h Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
23 TIE23 R/W 0h Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
22 TIE22 R/W 0h Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
21 TIE21 R/W 0h Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
20 TIE20 R/W 0h Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
19 TIE19 R/W 0h Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
18 TIE18 R/W 0h Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
17 TIE17 R/W 0h Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
16 TIE16 R/W 0h Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
15 TIE15 R/W 0h Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
14 TIE14 R/W 0h Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
13 TIE13 R/W 0h Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
12 TIE12 R/W 0h Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
11 TIE11 R/W 0h Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
10 TIE10 R/W 0h Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
9 TIE9 R/W 0h Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
8 TIE8 R/W 0h Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
7 TIE7 R/W 0h Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
6 TIE6 R/W 0h Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
5 TIE5 R/W 0h Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
4 TIE4 R/W 0h Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
3 TIE3 R/W 0h Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
2 TIE2 R/W 0h Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
1 TIE1 R/W 0h Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable
0 TIE0 R/W 0h Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 Transmission interrupt disabled
1 Transmission interrupt enable

21.51 MCAN_TXBCIE (Offset = 70E4h) [Reset = 00000000h]

MCAN_TXBCIE is shown in Figure 21-51 and described in Table 21-53.

Return to the Summary Table.

MCAN Tx Buffer Cancellation Finished Interrupt Enable

Figure 21-51 MCAN_TXBCIE
31 30 29 28 27 26 25 24
CFIE31 CFIE30 CFIE29 CFIE28 CFIE27 CFIE26 CFIE25 CFIE24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
CFIE23 CFIE22 CFIE21 CFIE20 CFIE19 CFIE18 CFIE17 CFIE16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
CFIE15 CFIE14 CFIE13 CFIE12 CFIE11 CFIE10 CFIE9 CFIE8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CFIE7 CFIE6 CFIE5 CFIE4 CFIE3 CFIE2 CFIE1 CFIE0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 21-53 MCAN_TXBCIE Field Descriptions
Bit Field Type Reset Description
31 CFIE31 R/W 0h Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
30 CFIE30 R/W 0h Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
29 CFIE29 R/W 0h Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
28 CFIE28 R/W 0h Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
27 CFIE27 R/W 0h Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
26 CFIE26 R/W 0h Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
25 CFIE25 R/W 0h Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
24 CFIE24 R/W 0h Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
23 CFIE23 R/W 0h Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
22 CFIE22 R/W 0h Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
21 CFIE21 R/W 0h Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
20 CFIE20 R/W 0h Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
19 CFIE19 R/W 0h Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
18 CFIE18 R/W 0h Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
17 CFIE17 R/W 0h Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
16 CFIE16 R/W 0h Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
15 CFIE15 R/W 0h Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
14 CFIE14 R/W 0h Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
13 CFIE13 R/W 0h Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
12 CFIE12 R/W 0h Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
11 CFIE11 R/W 0h Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
10 CFIE10 R/W 0h Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
9 CFIE9 R/W 0h Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
8 CFIE8 R/W 0h Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
7 CFIE7 R/W 0h Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
6 CFIE6 R/W 0h Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
5 CFIE5 R/W 0h Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
4 CFIE4 R/W 0h Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
3 CFIE3 R/W 0h Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
2 CFIE2 R/W 0h Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
1 CFIE1 R/W 0h Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled
0 CFIE0 R/W 0h Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
0 Cancellation finished interrupt disabled
1 Cancellation finished interrupt enabled

21.52 MCAN_TXEFC (Offset = 70F0h) [Reset = 00000000h]

MCAN_TXEFC is shown in Figure 21-52 and described in Table 21-54.

Return to the Summary Table.

MCAN Tx Event FIFO Configuration

Figure 21-52 MCAN_TXEFC
31 30 29 28 27 26 25 24
RESERVED EFWM
R-0h R/WQ-0h
23 22 21 20 19 18 17 16
RESERVED EFS
R-0h R/WQ-0h
15 14 13 12 11 10 9 8
EFSA
R/WQ-0h
7 6 5 4 3 2 1 0
EFSA RESERVED
R/WQ-0h R-0h
Table 21-54 MCAN_TXEFC Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29-24 EFWM R/WQ 0h Event FIFO Watermark
0 Watermark interrupt disabled
1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW)
>32 Watermark interrupt disabled
23-22 RESERVED R 0h
21-16 EFS R/WQ 0h Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1.
0 Tx Event FIFO disabled
1-32 Number of Tx Event FIFO elements
>32 Values greater than 32 are interpreted as 32
15-2 EFSA R/WQ 0h Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address).
1-0 RESERVED R 0h

21.53 MCAN_TXEFS (Offset = 70F4h) [Reset = 00000000h]

MCAN_TXEFS is shown in Figure 21-53 and described in Table 21-55.

Return to the Summary Table.

MCAN Tx Event FIFO Status

Figure 21-53 MCAN_TXEFS
31 30 29 28 27 26 25 24
RESERVED TEFL EFF
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED EFPI
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED EFGI
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED EFFL
R-0h R-0h
Table 21-55 MCAN_TXEFS Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R 0h
25 TEFL R 0h Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
0 No Tx Event FIFO element lost
1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
24 EFF R 0h Event FIFO Full
0 Tx Event FIFO not full
1 Tx Event FIFO full
23-21 RESERVED R 0h
20-16 EFPI R 0h Event FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31.
15-13 RESERVED R 0h
12-8 EFGI R 0h Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31.
7-6 RESERVED R 0h
5-0 EFFL R 0h Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32.

21.54 MCAN_TXEFA (Offset = 70F8h) [Reset = 00000000h]

MCAN_TXEFA is shown in Figure 21-54 and described in Table 21-56.

Return to the Summary Table.

MCAN Tx Event FIFO Acknowledge

Figure 21-54 MCAN_TXEFA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EFAI
R-0h R/W-0h
Table 21-56 MCAN_TXEFA Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4-0 EFAI R/W 0h Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.

21.55 MCANSS_PID (Offset = 7200h) [Reset = 68E04901h]

MCANSS_PID is shown in Figure 21-55 and described in Table 21-57.

Return to the Summary Table.

MCAN Subsystem Revision Register

Figure 21-55 MCANSS_PID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCHEME MODULE_ID
R-1h R-8E0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJOR MINOR
R-1h R-1h
Table 21-57 MCANSS_PID Field Descriptions
Bit Field Type Reset Description
31-30 SCHEME R 1h PID Register Scheme
27-16 MODULE_ID R 8E0h Module Identification Number
10-8 MAJOR R 1h Major Revision of the MCAN Subsystem
5-0 MINOR R 1h Minor Revision of the MCAN Subsystem

21.56 MCANSS_CTRL (Offset = 7204h) [Reset = 00000008h]

MCANSS_CTRL is shown in Figure 21-56 and described in Table 21-58.

Return to the Summary Table.

MCAN Subsystem Control Register

Figure 21-56 MCANSS_CTRL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_EN AUTOWAKEUP WAKEUPREQEN DBGSUSP_FREE RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-1h R-0h
Table 21-58 MCANSS_CTRL Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R 0h
6 EXT_TS_CNTR_EN R/W 0h External Timestamp Counter Enable.
0 External timestamp counter disabled
1 External timestamp counter enabled
5 AUTOWAKEUP R/W 0h Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request.
0 Disable the automatic write to CCCR.INIT
1 Enable the automatic write to CCCR.INIT
4 WAKEUPREQEN R/W 0h Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity.
0 Disable wakeup request
1 Enables wakeup request
3 DBGSUSP_FREE R/W 1h Debug Suspend Free Bit. Enables debug suspend.
0 Honor debug suspend
1 Disregard debug suspend
2-0 RESERVED R 0h

21.57 MCANSS_STAT (Offset = 7208h) [Reset = 0000000Xh]

MCANSS_STAT is shown in Figure 21-57 and described in Table 21-59.

Return to the Summary Table.

MCAN Subsystem Status Register

Figure 21-57 MCANSS_STAT
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE_FDOE MEM_INIT_DONE RESET
R-0h R-X R-0h R-0h
Table 21-59 MCANSS_STAT Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h
2 ENABLE_FDOE R X Enable FD (Flexible Data-Rate) Configuration
Reflects the value of mcanss_enable_fdoe configuration port,
-h = mcanss_enable_fdoe.
1 MEM_INIT_DONE R 0h Memory Initialization Done.
0 Message RAM initialization is in progress
1 Message RAM is initialized for use
0 RESET R 0h Soft Reset Status.
0 Not in reset
1 Reset is in progress

21.58 MCANSS_ICS (Offset = 720Ch) [Reset = 00000000h]

MCANSS_ICS is shown in Figure 21-58 and described in Table 21-60.

Return to the Summary Table.

MCAN Subsystem Interrupt Clear Shadow Register

Figure 21-58 MCANSS_ICS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_OVFL
R-0h R-0/W1C-0h
Table 21-60 MCANSS_ICS Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EXT_TS_CNTR_OVFL R-0/W1C 0h External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0.
0 Write of '0' has no effect
1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit

21.59 MCANSS_IRS (Offset = 7210h) [Reset = 00000000h]

MCANSS_IRS is shown in Figure 21-59 and described in Table 21-61.

Return to the Summary Table.

MCAN Subsystem Interrupt Raw Satus Register

Figure 21-59 MCANSS_IRS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_OVFL
R-0h R/W1S-0h
Table 21-61 MCANSS_IRS Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EXT_TS_CNTR_OVFL R/W1S 0h External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit.
0 External timestamp counter has not overflowed
1 External timestamp counter has overflowed

When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1.

21.60 MCANSS_IECS (Offset = 7214h) [Reset = 00000000h]

MCANSS_IECS is shown in Figure 21-60 and described in Table 21-62.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Clear Shadow Register

Figure 21-60 MCANSS_IECS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_OVFL
R-0h R-0/W1C-0h
Table 21-62 MCANSS_IECS Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EXT_TS_CNTR_OVFL R-0/W1C 0h External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0.
0 Write of '0' has no effect
1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit

21.61 MCANSS_IE (Offset = 7218h) [Reset = 00000000h]

MCANSS_IE is shown in Figure 21-61 and described in Table 21-63.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Register

Figure 21-61 MCANSS_IE
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_OVFL
R-0h R/W1S-0h
Table 21-63 MCANSS_IE Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EXT_TS_CNTR_OVFL R/W1S 0h External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit.

21.62 MCANSS_IES (Offset = 721Ch) [Reset = 00000000h]

MCANSS_IES is shown in Figure 21-62 and described in Table 21-64.

Return to the Summary Table.

MCAN Subsystem Interrupt Enable Status

Figure 21-62 MCANSS_IES
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_CNTR_OVFL
R-0h R-0h
Table 21-64 MCANSS_IES Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EXT_TS_CNTR_OVFL R 0h External Timestamp Counter Overflow Interrupt Enable Status. To set, use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear, use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit.
0 External timestamp counter overflow interrupt is not enabled
1 External timestamp counter overflow interrupt is enabled

21.63 MCANSS_EOI (Offset = 7220h) [Reset = 00000000h]

MCANSS_EOI is shown in Figure 21-63 and described in Table 21-65.

Return to the Summary Table.

MCAN Subsystem End of Interrupt

Figure 21-63 MCANSS_EOI
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI
R-0h R-0/W1S-0h
Table 21-65 MCANSS_EOI Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 EOI R-0/W1S 0h End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated.
0x00 External TS Interrupt is cleared
0x01 MCAN(0) interrupt is cleared
0x02 MCAN(1) interrupt is cleared
Other writes are ignored.

21.64 MCANSS_EXT_TS_PRESCALER (Offset = 7224h) [Reset = 00000000h]

MCANSS_EXT_TS_PRESCALER is shown in Figure 21-64 and described in Table 21-66.

Return to the Summary Table.

MCAN Subsystem External Timestamp Prescaler 0

Figure 21-64 MCANSS_EXT_TS_PRESCALER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PRESCALER
R-0h R/W-0h
Table 21-66 MCANSS_EXT_TS_PRESCALER Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
23-0 PRESCALER R/W 0h External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001.

21.65 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR (Offset = 7228h) [Reset = 00000000h]

MCANSS_EXT_TS_UNSERVICED_INTR_CNTR is shown in Figure 21-65 and described in Table 21-67.

Return to the Summary Table.

MCAN Subsystem External Timestamp Unserviced Interrupts Counter

Figure 21-65 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EXT_TS_INTR_CNTR
R-0h R-0h
Table 21-67 MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4-0 EXT_TS_INTR_CNTR R 0h External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt.

The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field.

21.66 MCANERR_REV (Offset = 7400h) [Reset = 66A0EA00h]

MCANERR_REV is shown in Figure 21-66 and described in Table 21-68.

Return to the Summary Table.

MCAN Error Aggregator Revision Register

Figure 21-66 MCANERR_REV
31 30 29 28 27 26 25 24
SCHEME MODULE_ID
R-1h R-6A0h
23 22 21 20 19 18 17 16
MODULE_ID
R-6A0h
15 14 13 12 11 10 9 8
REVMAJ
R-2h
7 6 5 4 3 2 1 0
REVMIN
R-0h
Table 21-68 MCANERR_REV Field Descriptions
Bit Field Type Reset Description
31-30 SCHEME R 1h PID Register Scheme
27-16 MODULE_ID R 6A0h Module Identification Number
10-8 REVMAJ R 2h Major Revision of the Error Aggregator
5-0 REVMIN R 0h Minor Revision of the Error Aggregator

21.67 MCANERR_VECTOR (Offset = 7408h) [Reset = 00000000h]

MCANERR_VECTOR is shown in Figure 21-67 and described in Table 21-69.

Return to the Summary Table.

Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.

Figure 21-67 MCANERR_VECTOR
31 30 29 28 27 26 25 24
RESERVED RD_SVBUS_DONE
R-0h R-0h
23 22 21 20 19 18 17 16
RD_SVBUS_ADDRESS
R/W-0h
15 14 13 12 11 10 9 8
RD_SVBUS RESERVED ECC_VECTOR
R-0/W1S-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
ECC_VECTOR
R/W-0h
Table 21-69 MCANERR_VECTOR Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R 0h
24 RD_SVBUS_DONE R 0h Read Completion Flag
23-16 RD_SVBUS_ADDRESS R/W 0h Read Address Offset
15 RD_SVBUS R-0/W1S 0h Read Trigger
14-11 RESERVED R 0h
10-0 ECC_VECTOR R/W 0h ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address.
0x000 Message RAM ECC controller is selected
Others Reserved (do not use)

Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing.

21.68 MCANERR_STAT (Offset = 740Ch) [Reset = 00000002h]

MCANERR_STAT is shown in Figure 21-68 and described in Table 21-70.

Return to the Summary Table.

MCAN Error Misc Status

Figure 21-68 MCANERR_STAT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUM_RAMS
R-0h R-2h
Table 21-70 MCANERR_STAT Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10-0 NUM_RAMS R 2h Number of RAMs. Number of ECC RAMs serviced by the aggregator.

21.69 MCANERR_WRAP_REV (Offset = 7410h) [Reset = 66A46A02h]

MCANERR_WRAP_REV is shown in Figure 21-69 and described in Table 21-71.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-69 MCANERR_WRAP_REV
31 30 29 28 27 26 25 24
SCHEME MODULE_ID
R-1h R-6A4h
23 22 21 20 19 18 17 16
MODULE_ID
R-6A4h
15 14 13 12 11 10 9 8
REVMAJ
R-2h
7 6 5 4 3 2 1 0
REVMIN
R-2h
Table 21-71 MCANERR_WRAP_REV Field Descriptions
Bit Field Type Reset Description
31-30 SCHEME R 1h PID Register Scheme
27-16 MODULE_ID R 6A4h Module Identification Number
10-8 REVMAJ R 2h Major Revision of the Error Aggregator
5-0 REVMIN R 2h Minor Revision of the Error Aggregator

21.70 MCANERR_CTRL (Offset = 7414h) [Reset = 00000187h]

MCANERR_CTRL is shown in Figure 21-70 and described in Table 21-72.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-70 MCANERR_CTRL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CHECK_SVBUS_TIMEOUT
R-0h R/W-1h
7 6 5 4 3 2 1 0
RESERVED ERROR_ONCE FORCE_N_ROW FORCE_DED FORCE_SEC ENABLE_RMW ECC_CHECK ECC_ENABLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h
Table 21-72 MCANERR_CTRL Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 CHECK_SVBUS_TIMEOUT R/W 1h Enables Serial VBUS timeout mechanism
7 RESERVED R 0h
6 ERROR_ONCE R/W 0h If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error.
5 FORCE_N_ROW R/W 0h Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads.
4 FORCE_DED R/W 0h Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
3 FORCE_SEC R/W 0h Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit.
2 ENABLE_RMW R/W 1h Enable read-modify-write on partial word writes
1 ECC_CHECK R/W 1h Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'.
0 ECC_ENABLE R/W 1h Enable ECC Generation

21.71 MCANERR_ERR_CTRL1 (Offset = 7418h) [Reset = 00000000h]

MCANERR_ERR_CTRL1 is shown in Figure 21-71 and described in Table 21-73.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-71 MCANERR_ERR_CTRL1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_ROW
R/W-0h
Table 21-73 MCANERR_ERR_CTRL1 Field Descriptions
Bit Field Type Reset Description
31-0 ECC_ROW R/W 0h Row address where FORCE_SEC or FORCE_DED needs to be applied. This is ignored if FORCE_N_ROW is set.

21.72 MCANERR_ERR_CTRL2 (Offset = 741Ch) [Reset = 00000000h]

MCANERR_ERR_CTRL2 is shown in Figure 21-72 and described in Table 21-74.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-72 MCANERR_ERR_CTRL2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_BIT2 ECC_BIT1
R/W-0h R/W-0h
Table 21-74 MCANERR_ERR_CTRL2 Field Descriptions
Bit Field Type Reset Description
31-16 ECC_BIT2 R/W 0h Second column/data bit that needs to be flipped when FORCE_DED is set
15-0 ECC_BIT1 R/W 0h Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set

21.73 MCANERR_ERR_STAT1 (Offset = 7420h) [Reset = 00000000h]

MCANERR_ERR_STAT1 is shown in Figure 21-73 and described in Table 21-75.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-73 MCANERR_ERR_STAT1
31 30 29 28 27 26 25 24
ECC_BIT1
R-0h
23 22 21 20 19 18 17 16
ECC_BIT1
R-0h
15 14 13 12 11 10 9 8
CLR_CTRL_REG_ERROR RESERVED CLR_ECC_OTHER CLR_ECC_DED CLR_ECC_SEC
R/W1S-0h R-0h R/W1C-0h R/WD-0h R/WD-0h
7 6 5 4 3 2 1 0
CTRL_REG_ERROR RESERVED ECC_OTHER ECC_DED ECC_SEC
R/W1S-0h R-0h R/W1S-0h R/WI-0h R/WI-0h
Table 21-75 MCANERR_ERR_STAT1 Field Descriptions
Bit Field Type Reset Description
31-16 ECC_BIT1 R 0h ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error.
0 Bit 0 is in error
1 Bit 1 is in error
2 Bit 2 is in error
3 Bit 3 is in error
...
31 Bit 31 is in error
>32 Invalid
15 CLR_CTRL_REG_ERROR R/W1S 0h Writing a '1' clears the CTRL_REG_ERROR bit
14-13 RESERVED R 0h
12 CLR_ECC_OTHER R/W1C 0h Writing a '1' clears the ECC_OTHER bit.
11-10 CLR_ECC_DED R/WD 0h Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided.
9-8 CLR_ECC_SEC R/WD 0h Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided.
7 CTRL_REG_ERROR R/W1S 0h Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag.
6-5 RESERVED R 0h
4 ECC_OTHER R/W1S 0h SEC While Writeback Error Status
0 No SEC error while writeback pending
1 Indicates that successive single-bit errors have occurred while a writeback is still pending
3-2 ECC_DED R/WI 0h Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared.

0 No double-bit error detected
1 One double-bit error was detected
2 Two double-bit errors were detected
3 Three double-bit errors were detected

A write of a non-zero value to this bit field increments it by the value provided.
1-0 ECC_SEC R/WI 0h Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared.

0 No single-bit error detected
1 One single-bit error was detected and corrected
2 Two single-bit errors were detected and corrected
3 Three single-bit errors were detected and corrected

A write of a non-zero value to this bit field increments it by the value provided.

21.74 MCANERR_ERR_STAT2 (Offset = 7424h) [Reset = 00000000h]

MCANERR_ERR_STAT2 is shown in Figure 21-74 and described in Table 21-76.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-74 MCANERR_ERR_STAT2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_ROW
R-0h
Table 21-76 MCANERR_ERR_STAT2 Field Descriptions
Bit Field Type Reset Description
31-0 ECC_ROW R 0h Indicates the row address where the single or double-bit error occurred. This value is address offset/4.

21.75 MCANERR_ERR_STAT3 (Offset = 7428h) [Reset = 00000000h]

MCANERR_ERR_STAT3 is shown in Figure 21-75 and described in Table 21-77.

Return to the Summary Table.

This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register.

Figure 21-75 MCANERR_ERR_STAT3
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CLR_SVBUS_TIMEOUT RESERVED
R-0h R-0/W1C-0h R-0h
7 6 5 4 3 2 1 0
RESERVED SVBUS_TIMEOUT WB_PEND
R-0h R-0/W1S-0h R-0h
Table 21-77 MCANERR_ERR_STAT3 Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h
9 CLR_SVBUS_TIMEOUT R-0/W1C 0h Write 1 to clear the Serial VBUS Timeout Flag
8-2 RESERVED R 0h
1 SVBUS_TIMEOUT R-0/W1S 0h Serial VBUS Timeout Flag. Write 1 to set.
0 WB_PEND R 0h Delayed Write Back Pending Status
0 No write back pending
1 An ECC data correction write back is pending

21.76 MCANERR_SEC_EOI (Offset = 743Ch) [Reset = 00000000h]

MCANERR_SEC_EOI is shown in Figure 21-76 and described in Table 21-78.

Return to the Summary Table.

MCAN Single Error Corrected End of Interrupt Register

Figure 21-76 MCANERR_SEC_EOI
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EOI_WR
R-0h R-0/W1S-0h
Table 21-78 MCANERR_SEC_EOI Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EOI_WR R-0/W1S 0h Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host.

Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

21.77 MCANERR_SEC_STATUS (Offset = 7440h) [Reset = 00000000h]

MCANERR_SEC_STATUS is shown in Figure 21-77 and described in Table 21-79.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Status Register

Figure 21-77 MCANERR_SEC_STATUS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_PEND
R-0h R-0-0h
Table 21-79 MCANERR_SEC_STATUS Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_PEND R-0 0h Message RAM SEC Interrupt Pending
0 No SEC interrupt is pending
1 SEC interrupt is pending

21.78 MCANERR_SEC_ENABLE_SET (Offset = 7480h) [Reset = 00000000h]

MCANERR_SEC_ENABLE_SET is shown in Figure 21-78 and described in Table 21-80.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Enable Set Register

Figure 21-78 MCANERR_SEC_ENABLE_SET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_ENABLE_SET
R-0h R/W1S-0h
Table 21-80 MCANERR_SEC_ENABLE_SET Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_ENABLE_SET R/W1S 0h Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

21.79 MCANERR_SEC_ENABLE_CLR (Offset = 74C0h) [Reset = 00000000h]

MCANERR_SEC_ENABLE_CLR is shown in Figure 21-79 and described in Table 21-81.

Return to the Summary Table.

MCAN Single Error Corrected Interrupt Enable Clear Register

Figure 21-79 MCANERR_SEC_ENABLE_CLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_ENABLE_CLR
R-0h R/W1C-0h
Table 21-81 MCANERR_SEC_ENABLE_CLR Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_ENABLE_CLR R/W1C 0h Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

21.80 MCANERR_DED_EOI (Offset = 753Ch) [Reset = 00000000h]

MCANERR_DED_EOI is shown in Figure 21-80 and described in Table 21-82.

Return to the Summary Table.

MCAN Double Error Detected End of Interrupt Register

Figure 21-80 MCANERR_DED_EOI
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED EOI_WR
R-0h R-0/W1S-0h
Table 21-82 MCANERR_DED_EOI Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 EOI_WR R-0/W1S 0h Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host.

Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field.

21.81 MCANERR_DED_STATUS (Offset = 7540h) [Reset = 00000000h]

MCANERR_DED_STATUS is shown in Figure 21-81 and described in Table 21-83.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Status Register

Figure 21-81 MCANERR_DED_STATUS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_PEND
R-0h R-0-0h
Table 21-83 MCANERR_DED_STATUS Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_PEND R-0 0h Message RAM DED Interrupt Pending
0 No DED interrupt is pending
1 DED interrupt is pending

21.82 MCANERR_DED_ENABLE_SET (Offset = 7580h) [Reset = 00000000h]

MCANERR_DED_ENABLE_SET is shown in Figure 21-82 and described in Table 21-84.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Enable Set Register

Figure 21-82 MCANERR_DED_ENABLE_SET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_ENABLE_SET
R-0h R/W1S-0h
Table 21-84 MCANERR_DED_ENABLE_SET Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_ENABLE_SET R/W1S 0h Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

21.83 MCANERR_DED_ENABLE_CLR (Offset = 75C0h) [Reset = 00000000h]

MCANERR_DED_ENABLE_CLR is shown in Figure 21-83 and described in Table 21-85.

Return to the Summary Table.

MCAN Double Error Detected Interrupt Enable Clear Register

Figure 21-83 MCANERR_DED_ENABLE_CLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED MSGMEM_ENABLE_CLR
R-0h R/W1C-0h
Table 21-85 MCANERR_DED_ENABLE_CLR Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 MSGMEM_ENABLE_CLR R/W1C 0h Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value.

21.84 MCANERR_AGGR_ENABLE_SET (Offset = 7600h) [Reset = 00000000h]

MCANERR_AGGR_ENABLE_SET is shown in Figure 21-84 and described in Table 21-86.

Return to the Summary Table.

MCAN Error Aggregator Enable Set Register

Figure 21-84 MCANERR_AGGR_ENABLE_SET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE_TIMEOUT_SET ENABLE_PARITY_SET
R-0h R/W1S-0h R/W1S-0h
Table 21-86 MCANERR_AGGR_ENABLE_SET Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENABLE_TIMEOUT_SET R/W1S 0h Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value.
0 ENABLE_PARITY_SET R/W1S 0h Write 1 to enable parity errors. Reads return the corresponding enable bit's current value.

21.85 MCANERR_AGGR_ENABLE_CLR (Offset = 7604h) [Reset = 00000000h]

MCANERR_AGGR_ENABLE_CLR is shown in Figure 21-85 and described in Table 21-87.

Return to the Summary Table.

MCAN Error Aggregator Enable Clear Register

Figure 21-85 MCANERR_AGGR_ENABLE_CLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE_TIMEOUT_CLR ENABLE_PARITY_CLR
R-0h R/W1C-0h R/W1C-0h
Table 21-87 MCANERR_AGGR_ENABLE_CLR Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENABLE_TIMEOUT_CLR R/W1C 0h Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value.
0 ENABLE_PARITY_CLR R/W1C 0h Write 1 to disable parity errors. Reads return the corresponding enable bit's current value.

21.86 MCANERR_AGGR_STATUS_SET (Offset = 7608h) [Reset = 00000000h]

MCANERR_AGGR_STATUS_SET is shown in Figure 21-86 and described in Table 21-88.

Return to the Summary Table.

MCAN Error Aggregator Status Set Register

Figure 21-86 MCANERR_AGGR_STATUS_SET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SVBUS_TIMEOUT AGGR_PARITY_ERR
R-0h R/WI-0h R/WI-0h
Table 21-88 MCANERR_AGGR_STATUS_SET Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3-2 SVBUS_TIMEOUT R/WI 0h Aggregator Serial VBUS Timeout Error Status

2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared.
0 No timeout errors have occurred
1 One timeout error has occurred
2 Two timeout errors have occurred
3 Three timeout errors have occurred

A write of a non-zero value to this bit field increments it by the value provided.
1-0 AGGR_PARITY_ERR R/WI 0h Aggregator Parity Error Status

2-bit saturating counter of the number of parity errors that have occurred since last cleared.
0 No parity errors have occurred
1 One parity error has occurred
2 Two parity errors have occurred
3 Three parity errors have occurred

A write of a non-zero value to this bit field increments it by the value provided.

21.87 MCANERR_AGGR_STATUS_CLR (Offset = 760Ch) [Reset = 00000000h]

MCANERR_AGGR_STATUS_CLR is shown in Figure 21-87 and described in Table 21-89.

Return to the Summary Table.

MCAN Error Aggregator Status Clear Register

Figure 21-87 MCANERR_AGGR_STATUS_CLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SVBUS_TIMEOUT AGGR_PARITY_ERR
R-0h R/WD-0h R/WD-0h
Table 21-89 MCANERR_AGGR_STATUS_CLR Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3-2 SVBUS_TIMEOUT R/WD 0h Aggregator Serial VBUS Timeout Error Status

2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared.
0 No timeout errors have occurred
1 One timeout error has occurred
2 Two timeout errors have occurred
3 Three timeout errors have occurred

A write of a non-zero value to this bit field decrements it by the value provided.
1-0 AGGR_PARITY_ERR R/WD 0h Aggregator Parity Error Status

2-bit saturating counter of the number of parity errors that have occurred since last cleared.
0 No parity errors have occurred
1 One parity error has occurred
2 Two parity errors have occurred
3 Three parity errors have occurred

A write of a non-zero value to this bit field decrements it by the value provided.

21.88 IIDX (Offset = 7820h) [Reset = 00000000h]

IIDX is shown in Figure 21-88 and described in Table 21-90.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 21-88 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 21-90 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
00h = No interrupt pending.
1h = MCAN Interrupt Line 0 interrupt pending.
2h = MCAN Interrupt Line 1 interrupt pending.
3h = Message RAM SEC (Single Error Correction) interrupt pending.
4h = Message RAM DED (Double Error Detection) interrupt pending.
5h = External Timestamp Counter Overflow interrupt pending.
6h = Clock Stop Wake Up interrupt pending.

21.89 IMASK (Offset = 7828h) [Reset = 00000000h]

IMASK is shown in Figure 21-89 and described in Table 21-91.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 21-89 IMASK
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP EXT_TS_CNTR_OVFL DED SEC INTL1 INTL0
R-0h -0 -0 -0 -0 -0 -0
Table 21-91 IMASK Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 WAKEUP R/W 0h Clock Stop Wake Up interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
4 EXT_TS_CNTR_OVFL R/W 0h External Timestamp Counter Overflow interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
3 DED R/W 0h Massage RAM DED interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2 SEC R/W 0h Message RAM SEC interrupt mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1 INTL1 R/W 0h MCAN Interrupt Line 1 mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0 INTL0 R/W 0h MCAN Interrupt Line 0 mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

21.90 RIS (Offset = 7830h) [Reset = 00000000h]

RIS is shown in Figure 21-90 and described in Table 21-92.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 21-90 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP EXT_TS_CNTR_OVFL DED SEC INTL1 INTL0
R-0h -0 -0 -0 -0 -0 -0
Table 21-92 RIS Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 WAKEUP R 0h Clock Stop Wake Up interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
4 EXT_TS_CNTR_OVFL R 0h External Timestamp Counter Overflow interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
3 DED R 0h Message RAM DED interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
2 SEC R 0h Message RAM SEC interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
1 INTL1 R 0h MCAN Interrupt Line 1.
0h = Interrupt did not occur
1h = Interrupt occured
0 INTL0 R 0h MCAN Interrupt Line 0.
0h = Interrupt did not occur
1h = Interrupt occured

21.91 MIS (Offset = 7838h) [Reset = 00000000h]

MIS is shown in Figure 21-91 and described in Table 21-93.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 21-91 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP EXT_TS_CNTR_OVFL DED SEC INTL1 INTL0
R-0h -0 -0 -0 -0 -0 -0
Table 21-93 MIS Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 WAKEUP R 0h Masked Clock Stop Wake Up interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
4 EXT_TS_CNTR_OVFL R 0h Masked External Timestamp Counter Overflow interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
3 DED R 0h Masked Message RAM DED interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
2 SEC R 0h Masked Message RAM SEC interrupt.
0h = Interrupt did not occur
1h = Interrupt occured
1 INTL1 R 0h Masked MCAN Interrupt Line 1.
0h = Interrupt did not occur
1h = Interrupt occured
0 INTL0 R 0h Masked MCAN Interrupt Line 0.
0h = Interrupt did not occur
1h = Interrupt occured

21.92 ISET (Offset = 7840h) [Reset = 00000000h]

ISET is shown in Figure 21-92 and described in Table 21-94.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 21-92 ISET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP EXT_TS_CNTR_OVFL DED SEC INTL1 INTL0
R-0h -0 -0 -0 -0 -0 -0
Table 21-94 ISET Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 WAKEUP W 0h Set Clock Stop Wake Up interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
4 EXT_TS_CNTR_OVFL W 0h Set External Timestamp Counter Overflow interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
3 DED W 0h Set Message RAM DED interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
2 SEC W 0h Set Message RAM SEC interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
1 INTL1 W 0h Set MCAN Interrupt Line 1.
0h = Writing 0 has no effect
1h = Set Interrupt
0 INTL0 W 0h Set MCAN Interrupt Line 0.
0h = Writing 0 has no effect
1h = Set Interrupt

21.93 ICLR (Offset = 7848h) [Reset = 00000000h]

ICLR is shown in Figure 21-93 and described in Table 21-95.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 21-93 ICLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP EXT_TS_CNTR_OVFL DED SEC INTL1 INTL0
R-0h -0 -0 -0 -0 -0 -0
Table 21-95 ICLR Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 WAKEUP W 0h Clear Clock Stop Wake Up interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
4 EXT_TS_CNTR_OVFL W 0h Clear External Timestamp Counter Overflow interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
3 DED W 0h Clear Message RAM DED interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
2 SEC W 0h Clear Message RAM SEC interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
1 INTL1 W 0h Clear MCAN Interrupt Line 1.
0h = Writing 0 has no effect
1h = Clear Interrupt
0 INTL0 W 0h Clear MCAN Interrupt Line 0.
0h = Writing 0 has no effect
1h = Clear Interrupt

21.94 EVT_MODE (Offset = 78E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 21-94 and described in Table 21-96.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 21-94 EVT_MODE
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INT0_CFG
R-0h R-0h
Table 21-96 EVT_MODE Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1-0 INT0_CFG R 0h Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

21.95 DESC (Offset = 78FCh) [Reset = 00000000h]

DESC is shown in Figure 21-95 and described in Table 21-97.

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This register identifies the peripheral and its exact version.

Figure 21-95 DESC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODULEID
-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEATUREVER RESERVED MAJREV MINREV
-0 R-0h -0 -0
Table 21-97 DESC Field Descriptions
Bit Field Type Reset Description
31-16 MODULEID R 0x0 Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12 FEATUREVER R 0x0 Feature Set for the module *instance*
0h = MCAN module with CAN-FD mode enabled
<<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>>
1h = MCAN module with CAN-FD mode disabled
<<Internal Note: This is an in-IP paper spin variant. How does this map to the SYS_MCAN_ENABLE_FD choice value?>>
11-8 RESERVED R 0h
7-4 MAJREV R 0x0 Major rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0 MINREV R 0x0 Minor rev of the IP
0h = Smallest value
Fh = Highest possible value

21.96 MCANSS_CLKEN (Offset = 7900h) [Reset = 00000000h]

MCANSS_CLKEN is shown in Figure 21-96 and described in Table 21-98.

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MCAN module clock (functional clock and Vbusp to access MCAN module MMRs) enable register

<Internal note> This IP-specific MMR itself is not clock gated, as long as IP is enabled by the paper-spin configuration

Figure 21-96 MCANSS_CLKEN
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CLK_REQEN
R-0h -0
Table 21-98 MCANSS_CLKEN Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 CLK_REQEN RW 0x0 MCAN functional and MCAN/MCANSS MMR clock request enable bit

0h = MCAN module functional clock and Vbusp is not requested.
These clocks are gated to the MCAN module.
1h = Setting this bit requests MCAN module functional clock and Vbusp.
These clocks are not gated to MCAN module.

21.97 MCANSS_CLKDIV (Offset = 7904h) [Reset = 00000000h]

MCANSS_CLKDIV is shown in Figure 21-97 and described in Table 21-99.

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Needs to go to the Management apperture once available

Figure 21-97 MCANSS_CLKDIV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RATIO
R-0h R/W-0h
Table 21-99 MCANSS_CLKDIV Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1-0 RATIO R/W 0x0 Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS.
0h (R/W) = Divides input clock by 1
1h (R/W) = Divides input clock by 2
2h (R/W) = Divides input clock by 4
3h (R/W) = Divides input clock by 1

21.98 MCANSS_CLKCTL (Offset = 7908h) [Reset = 00000000h]

MCANSS_CLKCTL is shown in Figure 21-98 and described in Table 21-100.

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MCANSS clock stop control MMR.
<Internal note> Bus clock for the wrapper MMRs (including this MMR) is not gated by this register.

Figure 21-98 MCANSS_CLKCTL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED WKUP_GLTFLT_EN
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED WAKEUP_INT_EN RESERVED STOPREQ
R-0h R/W-0h R-0h -0
Table 21-100 MCANSS_CLKCTL Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 WKUP_GLTFLT_EN R/W 0h Setting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating.
0h = Disable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup).
1h = Enable glitch filter enable on RXD input when MCAN is in clock stop mode (waiting for event on RXD input for clock stop wakeup).
7-5 RESERVED R 0h
4 WAKEUP_INT_EN R/W 0h This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)
0h = Disable MCAN IP clock stop wakeup interrupt
1h = Enable MCAN IP clock stop wakeup interrupt
3-1 RESERVED R 0h
0 STOPREQ R/W 0h This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request.

Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details.

0h = Disable MCAN-SS clock stop request
1h = Enable MCAN-SS clock stop request

21.99 MCANSS_CLKSTS (Offset = 790Ch) [Reset = 00000000h]

MCANSS_CLKSTS is shown in Figure 21-99 and described in Table 21-101.

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MCANSS clock stop status register to indicate status of clock stop mechanism

Figure 21-99 MCANSS_CLKSTS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CCLKDONE
R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED STOPREQ_HW_OVR RESERVED CLKSTOP_ACKSTS
R-0h R-0h R-0h R-0h
Table 21-101 MCANSS_CLKSTS Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 CCLKDONE R 0h This bit indicates the status of MCAN contoller clock request from GPRCM.
0h = MCAN controller clock is not available to the MCAN IP.
1h = MCAN controller clock is enabled and available to the MCAN IP.
7-5 RESERVED R 0h
4 STOPREQ_HW_OVR R 0h MCANSS clock stop HW override status bit.

This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is triggered.
0h = MCANSS_CLKCTL.STOPREQ bit has not been cleared by HW.
1h = MCANSS_CLKCTL.STOPREQ bit has been cleared by HW.
3-1 RESERVED R 0h
0 CLKSTOP_ACKSTS R 0h Clock stop acknowledge status from MCAN IP
0h = No clock stop acknowledged.
1h = Clock stop has been acknowledged by MCAN IP; MCAN-SS may be clock gated by stopping both the CAN host and functional clocks.