SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 5-27 lists the memory-mapped registers for the MATHACL registers. All register offset addresses not listed in Table 5-27 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
800h | PWREN | Power Enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1100h | CTL | Control Register | Go | |
1118h | OP2 | Operand 2 register. | Go | |
111Ch | OP1 | Operand 1 Register | Go | |
1120h | RES1 | Result 1 Register | Go | |
1124h | RES2 | Result 2 Register | Go | |
1130h | STATUS | Status Register | Go | |
1140h | STATUSCLR | Status Flag Clear Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-28 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 5-3 and described in Table 5-29.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 5-4 and described in Table 5-30.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 5-5 and described in Table 5-31.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CTL is shown in Figure 5-6 and described in Table 5-32.
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Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | NUMITER | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SATEN | SFACTOR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | QVAL | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OPTYPE | FUNC | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | 0h | |
28-24 | NUMITER | R/W | 0h | Number of iterations, applicable if the function does the computations iteratively, for example sine/cosine/atan2/sqrt. Note: A value of 0 is interpreted as 31. |
23 | RESERVED | R/W | 0h | |
22 | SATEN | R/W | 0h | Saturation enable This bit is shared among DIV, SQUARE32, MPY32, MAC and SAC functions. When enabled, it will make the result to saturate to maximum value in case of an overflow event When disabled, the result will overflow to an unknown value. 0h = Saturation is disabled 1h = Saturation is enabled |
21-16 | SFACTOR | R/W | 0h | Scaling factor. In case of SQRT function, the input operand needs to be in a range. If not it has to be scaled to 2+/-n. This field should be written with the value 'n'. |
15-13 | RESERVED | R/W | 0h | |
12-8 | QVAL | R/W | 0h | Indicates the fractional bits in the operands, ranges from 0 to 31. Applicable to DIV function.
0h = Q0 operands 1h = Q1 operands 2h = Q2 operands 3h = Q3 operands 4h = Q4 operands 5h = Q5 operands 6h = Q6 operands 7h = Q7 operands 8h = Q8 operands 9h = Q9 operands Ah = Q10 operands Bh = Q11 operands Ch = Q12 operands Dh = Q13 operands Eh = Q14 operands Fh = Q15 operands 10h = Q16 operands 11h = Q17 operands 12h = Q18 operands 13h = Q19 operands 14h = Q20 operands 15h = Q21 operands 16h = Q22 operands 17h = Q23 operands 18h = Q24 operands 19h = Q25 operands 1Ah = Q26 operands 1Bh = Q27 operands 1Ch = Q28 operands 1Dh = Q29 operands 1Eh = Q30 operands 1Fh = Q31 operands |
7-6 | RESERVED | R/W | 0h | |
5 | OPTYPE | R/W | 0h | Operand type, could signed or unsigned. applicable to DIV function.
0h = Unsigned operands 1h = Signed operands. |
4-0 | FUNC | R/W | 0h | ULP_ADCHP Enable Conversions.
0h = No operation 1h = Sine and Cosine operation 2h = Arc tangent with x and y values as operands. 4h = Divide, the operands are numerator, denominator, and the divide type. Result is the quotient and reminder. 5h = Do square root. Operand is the number whoose square root needs to be computed. The number if outside the range needs to be scaled up down by 2 power 2n to bring it with in the range. 6h = 32-bit Multiply Result 7h = 32-bit square result 8h = 64-bit multiply result 9h = 64-bit multiply result Ah = Multiply and accumulate operation Bh = Square and accumulate operation |
OP2 is shown in Figure 5-7 and described in Table 5-33.
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Operand 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Operand 2 Register |
OP1 is shown in Figure 5-8 and described in Table 5-34.
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Operand 1 register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Operand 1 Register |
RES1 is shown in Figure 5-9 and described in Table 5-35.
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Result 1 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
RH/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | RH/W | 0h | Result 1 Register |
RES2 is shown in Figure 5-10 and described in Table 5-36.
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Result 2 Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
RH/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | RH/W | 0h | Result 2 Register |
STATUS is shown in Figure 5-11 and described in Table 5-37.
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Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BUSY | ||||||
R-0h | RH-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERR | OVF | UF | ||||
R-0h | RH-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | |
8 | BUSY | RH | 0h | MATHACL busy bit.
0h = Compute has completed. 1h = Compute ongoing |
7-4 | RESERVED | R | 0h | |
3-2 | ERR | RH | 0h | Incorrect inputs/outputs.
0h = No Error in computation. 1h = DIVBY0 error |
1 | OVF | R | 0h | Overflow bit for MPY32, SQUARE32, DIV, MAC, and SAC functions This bit will be set on overflow and will retain its value until cleared by writing 1 into CLR.CLR_OVF 0h = Overflow error. |
0 | UF | R | 0h | Underflow Flag
0h = No underflow error. 1h = Underflow error. |
STATUSCLR is shown in Figure 5-12 and described in Table 5-38.
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Clear register for clearing flags in STATUS register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLR_ERR | CLR_OVF | CLR_UF | ||||
W-0h | W-0h | W-0h | W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | W | 0h | |
2 | CLR_ERR | W | 0h | Write 1 to this bit to clear STATUS.ERR field
0h = Writing 0 has no effect 1h = Clear STATUS.ERR |
1 | CLR_OVF | W | 0h | Write 1 to this bit to clear STATUS.OVF bit
0h = Writing 0 has no effect 1h = Clear STATUS.OVF |
0 | CLR_UF | W | 0h | Write 1 to this bit to clear STATUS.UF bit
0h = Writing 0 has no effect 1h = Clear STATUS.UF |