SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 28-8 lists the memory-mapped registers for the DEBUGSS registers. All register offset addresses not listed in Table 28-8 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | TXD | Transmit data register | Go | |
1104h | TXCTL | Transmit control register | Go | |
1108h | RXD | Receive data register | Go | |
110Ch | RXCTL | Receive control register | Go | |
1200h | SPECIAL_AUTH | Special enable authorization register | Go | |
1210h | APP_AUTH | Application CPU0 authorization register | Go |
Complex bit access types are encoded to fit into small table cells. Table 28-9 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
IIDX is shown in Figure 28-2 and described in Table 28-10.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. 0xFF means no event pending. Interrupt 0x0 is the highest priority, 0x1 next highest, and 0xFE is the least priority. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it displays 0xFF.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt request 1h = TX interrupt 2h = RX interrupt 3h = Power-up interrupt. A debug session has started. 4h = Power-up interrupt. A debug session has started. |
IMASK is shown in Figure 28-3 and described in Table 28-11.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRDWNIFG | PWRUPIFG | RXIFG | TXIFG | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | PWRDWNIFG | R/W | 0h | Masks PWRDWNIFG in MIS register
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
2 | PWRUPIFG | R/W | 0h | Masks PWRUPIFG in MIS register
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
1 | RXIFG | R/W | 0h | Masks RXIFG in MIS register
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | TXIFG | R/W | 0h | Masks TXIFG in MIS register
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
RIS is shown in Figure 28-4 and described in Table 28-12.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRDWNIFG | PWRUPIFG | RXIFG | TXIFG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | PWRDWNIFG | R | 0h | Raw interrupt status for PWRDWNIFG
0h = PWRUPIFG did not occur 1h = PWRUPIFG occurred |
2 | PWRUPIFG | R | 0h | Raw interrupt status for PWRUPIFG
0h = PWRUPIFG did not occur 1h = PWRUPIFG occurred |
1 | RXIFG | R | 0h | Raw interrupt status for RXIFG
0h = RXIFG did not occur 1h = RXIFG occurred |
0 | TXIFG | R | 0h | Raw interrupt status for TXIFG
0h = TXIFG did not occur 1h = TXIFG occurred |
MIS is shown in Figure 28-5 and described in Table 28-13.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRDWNIFG | PWRUPIFG | RXIFG | TXIFG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | PWRDWNIFG | R | 0h | Masked interrupt status for PWRDWNIFG
0h = PWRUPIFG did not request an interrupt service routine 1h = PWRUPIFG requests an interrupt service routine |
2 | PWRUPIFG | R | 0h | Masked interrupt status for PWRUPIFG
0h = PWRUPIFG did not request an interrupt service routine 1h = PWRUPIFG requests an interrupt service routine |
1 | RXIFG | R | 0h | Masked interrupt status for RXIFG
0h = RXIFG did not request an interrupt service routine 1h = RXIFG requests an interrupt service routine |
0 | TXIFG | R | 0h | Masked interrupt status for TXIFG
0h = TXIFG did not request an interrupt service routine 1h = TXIFG requests an interrupt service routine |
ISET is shown in Figure 28-6 and described in Table 28-14.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRDWNIFG | PWRUPIFG | RXIFG | TXIFG | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | PWRDWNIFG | W | 0h | Sets PWRDWNIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to PWRUPIFG is set |
2 | PWRUPIFG | W | 0h | Sets PWRUPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to PWRUPIFG is set |
1 | RXIFG | W | 0h | Sets RXIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to RXIFG is set |
0 | TXIFG | W | 0h | Sets TXIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to TXIFG is set |
ICLR is shown in Figure 28-7 and described in Table 28-15.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRDWNIFG | PWRUPIFG | RXIFG | TXIFG | |||
W-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | PWRDWNIFG | W | 0h | Clears PWRDWNIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to PWRUPIFG is cleared |
2 | PWRUPIFG | W | 0h | Clears PWRUPIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to PWRUPIFG is cleared |
1 | RXIFG | W | 0h | Clears RXIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to RXIFG is cleared |
0 | TXIFG | W | 0h | Clears TXIFG in RIS register
0h = Writing a 0 has no effect 1h = RIS bit corresponding to TXIFG is cleared |
EVT_MODE is shown in Figure 28-8 and described in Table 28-16.
Return to the Summary Table.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT0_CFG | ||||||
R- | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1-0 | INT0_CFG | R | 1h | Event line mode select for peripheral events
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 28-9 and described in Table 28-17.
Return to the Summary Table.
This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-340h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | INSTNUM | MAJREV | MINREV | ||||||||||||
R-0h | R-0h | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 340h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance* |
11-8 | INSTNUM | R | 0h | Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances |
7-4 | MAJREV | R | 0h | Major rev of the IP |
3-0 | MINREV | R | 0h | Minor rev of the IP |
TXD is shown in Figure 28-10 and described in Table 28-18.
Return to the Summary Table.
This register is used for data transfers from external debug tools to the DSSM module. The register is written by the debug tool and read by the CPU.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_DATA | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_DATA | R | 0h | Contains data written by an external debug tool to the SEC-AP TXDATA register |
TXCTL is shown in Figure 28-11 and described in Table 28-19.
Return to the Summary Table.
Transmit control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TRANSMIT_FLAGS | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TRANSMIT_FLAGS | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TRANSMIT_FLAGS | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRANSMIT_FLAGS | TRANSMIT | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | TRANSMIT_FLAGS | R | 0h | Generic TX flags that can be set by external debug tool. Functionality is defined by SW. |
0 | TRANSMIT | R | 0h | Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field. 0h = TXD is empty 1h = TXD is full |
RXD is shown in Figure 28-12 and described in Table 28-20.
Return to the Summary Table.
Receive data register. This register contains the data written by the CPU.
This data is read by external debug tool.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_DATA | R/W | 0h | Contains data written by SM/OW. |
RXCTL is shown in Figure 28-13 and described in Table 28-21.
Return to the Summary Table.
Receive control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RECEIVE_FLAGS | RECEIVE | ||||||
R/W-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-1 | RECEIVE_FLAGS | R/W | 0h | Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW. |
0 | RECEIVE | R | 0h | Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field. 0h = RXD empty 1h = RXD full |
SPECIAL_AUTH is shown in Figure 28-14 and described in Table 28-22.
Return to the Summary Table.
This register is used to control ET-AP, DFT-TAP, SWD, CFG-AP and SEC-AP.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRAPEN | AHBAPEN | CFGAPEN | ETAPEN | DFTAPEN | SWDPORTEN | SECAPEN |
R-0h | R-0h | R-0h | R-1h | R-0h | R-0h | R-1h | R-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | |
6 | PWRAPEN | R | 0h | An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable PWR-AP 1h = Enable PWR-AP |
5 | AHBAPEN | R | 0h | Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation.
0h = Disable AHB-AP 1h = Enable AHB-AP |
4 | CFGAPEN | R | 1h | An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP.
0h = Disable CFG-AP 1h = Enable CFG-AP |
3 | ETAPEN | R | 0h | An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable ET+ -AP 1h = Enable ET+ -AP |
2 | DFTAPEN | R | 0h | An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.
0h = Disable DFT-TAP 1h = Enable DFT-TAP |
1 | SWDPORTEN | R | 1h | When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access. 0h = Disable SWD port 1h = Enable SWD port |
0 | SECAPEN | R | 1h | An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP.
0h = Disable SEC-AP 1h = Enable SEC-AP |
APP_AUTH is shown in Figure 28-15 and described in Table 28-23.
Return to the Summary Table.
This register is used to control DBGEN, NIDEN, SPIDEN, and SPNIDEN of Application CPU0.
DBGEN, NIDEN are further processed by DSW based on Active and Debug IPF ID.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPNIDEN | SPIDEN | NIDEN | DBGEN | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | SPNIDEN | R | 0h | Secure non-invasive debug enable. 0h = Invasive debug disabled 1h = Invasive debug enabled |
2 | SPIDEN | R | 0h | Secure invasive debug enable. 0h = Invasive debug disabled 1h = Invasive debug enabled |
1 | NIDEN | R | 0h | Controls non-invasive debug enable.
0h = Non-invasive debug disabled 1h = Non-invasive debug enabled |
0 | DBGEN | R | 0h | Controls invasive debug enable. 0h = Invasive debug disabled 1h = Invasive debug enabled |