SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 6-12 lists the memory-mapped registers for the FLASHCTL registers. All register offset addresses not listed in Table 6-12 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
1020h | IIDX | Interrupt Index Register | Go | |
1028h | IMASK | Interrupt Mask Register | Go | |
1030h | RIS | Raw Interrupt Status Register | Go | |
1038h | MIS | Masked Interrupt Status Register | Go | |
1040h | ISET | Interrupt Set Register | Go | |
1048h | ICLR | Interrupt Clear Register | Go | |
1100h | CMDEXEC | Command Execute Register | Go | |
1104h | CMDTYPE | Command Type Register | Go | |
1108h | CMDCTL | Command Control Register | Go | |
1120h | CMDADDR | Command Address Register | Go | |
1124h | CMDBYTEN | Command Program Byte Enable Register | Go | |
112Ch | CMDDATAINDEX | Command Data Index Register | Go | |
1130h | CMDDATA0 | Command Data Register 0 | Go | |
1134h | CMDDATA1 | Command Data Register 1 | Go | |
1138h | CMDDATA2 | Command Data Register 2 | Go | |
113Ch | CMDDATA3 | Command Data Register Bits 127:96 | Go | |
1140h | CMDDATA4 | Command Data Register 4 | Go | |
1144h | CMDDATA5 | Command Data Register 5 | Go | |
1148h | CMDDATA6 | Command Data Register 6 | Go | |
114Ch | CMDDATA7 | Command Data Register 7 | Go | |
1150h | CMDDATA8 | Command Data Register 8 | Go | |
1154h | CMDDATA9 | Command Data Register 9 | Go | |
1158h | CMDDATA10 | Command Data Register 10 | Go | |
115Ch | CMDDATA11 | Command Data Register 11 | Go | |
1160h | CMDDATA12 | Command Data Register 12 | Go | |
1164h | CMDDATA13 | Command Data Register 13 | Go | |
1168h | CMDDATA14 | Command Data Register 14 | Go | |
116Ch | CMDDATA15 | Command Data Register 15 | Go | |
1170h | CMDDATA16 | Command Data Register 16 | Go | |
1174h | CMDDATA17 | Command Data Register 17 | Go | |
1178h | CMDDATA18 | Command Data Register 18 | Go | |
117Ch | CMDDATA19 | Command Data Register 19 | Go | |
1180h | CMDDATA20 | Command Data Register 20 | Go | |
1184h | CMDDATA21 | Command Data Register 21 | Go | |
1188h | CMDDATA22 | Command Data Register 22 | Go | |
118Ch | CMDDATA23 | Command Data Register 23 | Go | |
1190h | CMDDATA24 | Command Data Register 24 | Go | |
1194h | CMDDATA25 | Command Data Register 25 | Go | |
1198h | CMDDATA26 | Command Data Register 26 | Go | |
119Ch | CMDDATA27 | Command Data Register 27 | Go | |
11A0h | CMDDATA28 | Command Data Register 28 | Go | |
11A4h | CMDDATA29 | Command Data Register 29 | Go | |
11A8h | CMDDATA30 | Command Data Register 30 | Go | |
11ACh | CMDDATA31 | Command Data Register 31 | Go | |
11B0h | CMDDATAECC0 | Command Data Register ECC 0 | Go | |
11B4h | CMDDATAECC1 | Command Data Register ECC 1 | Go | |
11B8h | CMDDATAECC2 | Command Data Register ECC 2 | Go | |
11BCh | CMDDATAECC3 | Command Data Register ECC 3 | Go | |
11C0h | CMDDATAECC4 | Command Data Register ECC 4 | Go | |
11C4h | CMDDATAECC5 | Command Data Register ECC 5 | Go | |
11C8h | CMDDATAECC6 | Command Data Register ECC 6 | Go | |
11CCh | CMDDATAECC7 | Command Data Register ECC 7 | Go | |
11D0h | CMDWEPROTA | Command Write Erase Protect A Register | Go | |
11D4h | CMDWEPROTB | Command Write Erase Protect B Register | Go | |
11D8h | CMDWEPROTC | Command Write Erase Protect C Register | Go | |
1210h | CMDWEPROTNM | Command Write Erase Protect Non-Main Register | Go | |
13B4h | CFGPCNT | Pulse Counter Configuration Register | Go | |
13D0h | STATCMD | Command Status Register | Go | |
13D4h | STATADDR | Address Status Register | Go | |
13D8h | STATPCNT | Pulse Count Status Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-13 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
IIDX is shown in Figure 6-4 and described in Table 6-14.
Return to the Summary Table.
The interrupt index (IIDX) register provides the index of the highest priority pending and enabled interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 0h | Index corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0h (R/W) = No Interrupt Pending 1h (R/W) = DONE Interrupt Pending |
IMASK is shown in Figure 6-5 and described in Table 6-15.
Return to the Summary Table.
The interrupt mask (IMASK) register holds the current interrupt mask settings.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | DONE | R/W | 0h | Enable or disable the DONE interrupt.
0h (R/W) = Interrupt is masked out 1h (R/W) = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
RIS is shown in Figure 6-6 and described in Table 6-16.
Return to the Summary Table.
The raw interrupt status (RIS) register holds the current raw interrupt status.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | DONE | R | 0h | Raw status of the DONE interrupt.
0h (R/W) = Interrupt did not occur 1h (R/W) = Interrupt occurred |
MIS is shown in Figure 6-7 and described in Table 6-17.
Return to the Summary Table.
The masked interrupt status (MIS) register holds the current masked interrupt status.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | DONE | R | 0h | Masked status of the DONE interrupt.
0h (R/W) = Masked interrupt did not occur 1h (R/W) = Masked interrupt occurred |
ISET is shown in Figure 6-8 and described in Table 6-18.
Return to the Summary Table.
The interrupt set (ISET) register may be used to set an interrupt to pending from software.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ||||||
W-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | Reserved |
0 | DONE | W | 0h | Set the DONE interrupt.
0h (R/W) = Writing a 0 has no effect 1h (R/W) = Set RIS bit |
ICLR is shown in Figure 6-9 and described in Table 6-19.
Return to the Summary Table.
The interrupt clear (ICLR) register may be used to clear a pending interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ||||||
W-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | Reserved |
0 | DONE | W | 0h | Clear the DONE interrupt.
0h (R/W) = Writing a 0 has no effect 1h (R/W) = Clear RIS bit |
CMDEXEC is shown in Figure 6-10 and described in Table 6-20.
Return to the Summary Table.
Command Execute Register
Initiates execution of the command specified in the CMDTYPE register. This register is blocked for writes after being written to 1 and prior to STATCMD.DONE being set by hardware. Hardware clears this register after the processing of the command has completed.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | VAL | R/W | 0h | Command Execute value
Initiates execution of the command specified in the CMDTYPE register.
0h (R/W) = Command will not execute or is not executing in hardware 1h (R/W) = Command will execute or is executing in hardware |
CMDTYPE is shown in Figure 6-11 and described in Table 6-21.
Return to the Summary Table.
Command Type Register
Specifies the type of command to be executed by hardware. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIZE | RESERVED | COMMAND | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | 0h | Reserved |
6-4 | SIZE | R/W | 0h | Command size
0h (R/W) = Operate on 1 flash word 1h (R/W) = Operate on 2 flash words 2h (R/W) = Operate on 4 flash words 3h (R/W) = Operate on 8 flash words 4h (R/W) = Operate on a flash sector 5h (R/W) = Operate on an entire flash bank |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | COMMAND | R/W | 0h | Command type
0h (R/W) = No Operation 1h (R/W) = Program 2h (R/W) = Erase 3h (R/W) = Read Verify - Perform a standalone read verify operation. 6h (R/W) = Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD |
CMDCTL is shown in Figure 6-12 and described in Table 6-22.
Return to the Summary Table.
Command Control Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | SSERASEDIS | RESERVED | ECCGENOVR | ADDRXLATEOVR | ||
R/W-0h | R/W- | R/W-0h | R/W- | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | REGIONSEL | RESERVED | ||||
R/W- | R/W-0h | R/W-0h | R/W- | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BANKSEL | RESERVED | |||||
R/W- | R/W-0h | R/W- | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R/W | 0h | Reserved |
21 | RESERVED | R/W | 0h | |
20 | SSERASEDIS | R/W | 0h | Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used
for all erase pulses.
By default, this bit is reset, meaning that the VHV voltage will be stepped during
successive erase pulses. The step count, step voltage, begin and end voltages
are all hard-wired.
0h (R/W) = Enable 1h (R/W) = Disable |
19-18 | RESERVED | R/W | 0h | |
17 | ECCGENOVR | R/W | 0h | Override hardware generation of ECC data for program. Use data written to
CMDDATAECC*.
0h (R/W) = Do not override 1h (R/W) = Override |
16 | ADDRXLATEOVR | R/W | 0h | Override hardware address translation of address in CMDADDR from a system address to the corresponding bank address and bank ID. When set, CMDADDR will be used directly as the bank address, CMDCTL.REGIONSEL will be used directly as the region ID, and CMDCTL.BANKSEL will be used directly as the bank ID (if the device contains multiple banks).
0h (R/W) = Do not override 1h (R/W) = Override |
15-14 | RESERVED | R/W | 0h | |
13 | RESERVED | R/W | 0h | Reserved |
12-9 | REGIONSEL | R/W | 0h | Bank Region
A specific region ID can be written to this field to indicate to which region an
operation should be applied if CMDCTL.ADDRXLATEOVR is set.
1h (R/W) = Main Region 2h (R/W) = Non-Main Region |
8-5 | RESERVED | R/W | 0h | |
4 | BANKSEL | R/W | 0h | Bank Select
A specific Bank ID can be written to this field to indicate to which bank an
operation should be applied if CMDCTL.ADDRXLATEOVR is set.
1h (R/W) = Bank 0 2h (R/W) = Bank 1 4h (R/W) = Bank 2 8h (R/W) = Bank 3 10h (R/W) = Bank 4 |
3-0 | RESERVED | R/W | 0h |
CMDADDR is shown in Figure 6-13 and described in Table 6-23.
Return to the Summary Table.
Command Address Register:
This register forms the target address of a command. The use cases are as follows:
1) For single-word program, this address indicates the flash bank word to be programmed.
2) For multi-word program, this address indicates the first flash bank address for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
5) For read verify, the address indications follow program/erase listed above.
Note the address written to this register will be submitted for translation to the flash address translation interface, and the translated address will be used to access the bank. However, if the CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Address value
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDBYTEN is shown in Figure 6-14 and described in Table 6-24.
Return to the Summary Table.
Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to be programmed, a 1 must be written to the corresponding bit in this register. Normally, all bits are written to 1, allowing program of full flash words. However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit or 64-bit portions of a flash word.
In addition, the read verify command will ignore data bytes read from the flash in its comparison if the corresponding CMDBYTEN bit is 0.
For 64-bit flash word size devices, the CMDBYTEN register uses BIT7-0 to enable each data byte and BIT8 to enable the ECC code byte.
For 128-bit flash word size devices, the CMDBYTEN register uses BIT15-0 to enable each data byte and BIT17-16 to enable each ECC code byte.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is written to all 0 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | VAL | |||||||||||||||||||||||||||||
R/W-0h | R/W- | R/W-0h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | Reserved |
17-8 | RESERVED | R/W | 0h | |
7-0 | VAL | R/W | 0h | Command Byte Enable value.
A 1-bit per flash word byte value is placed in this register.
0h = Minimum value of [VAL] 0003FFFFh = Maximum value of [VAL] |
CMDDATAINDEX is shown in Figure 6-15 and described in Table 6-25.
Return to the Summary Table.
Command Program Data Index Register:
When multiple data registers are available for multi-word program, this register can be written with an index which points to one of the data registers. When a write to CMDDATA* is done, the data will be written to the physical data register indexed by the value in this register.
Up to 8 data registers can be present, so this register can be written with 0x0 to 0x7. If less than 8 data registers are present, successive MSB bits of this register are ignored when indexing the CMDDATA* registers.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | Reserved |
2-0 | VAL | R/W | 0h | Data register index
0h = Minimum value of [VAL] 7h = Maximum value of [VAL] |
CMDDATA0 is shown in Figure 6-16 and described in Table 6-26.
Return to the Summary Table.
Command Data Register 0
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA1 is shown in Figure 6-17 and described in Table 6-27.
Return to the Summary Table.
Command Data Register 1
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA2 is shown in Figure 6-18 and described in Table 6-28.
Return to the Summary Table.
Command Data Register 2
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA3 is shown in Figure 6-19 and described in Table 6-29.
Return to the Summary Table.
Command Data Register 3
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA4 is shown in Figure 6-20 and described in Table 6-30.
Return to the Summary Table.
Command Data Register 4
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
T
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA5 is shown in Figure 6-21 and described in Table 6-31.
Return to the Summary Table.
Command Data Register 5
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA6 is shown in Figure 6-22 and described in Table 6-32.
Return to the Summary Table.
Command Data Register 6
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA7 is shown in Figure 6-23 and described in Table 6-33.
Return to the Summary Table.
Command Data Register 7
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA8 is shown in Figure 6-24 and described in Table 6-34.
Return to the Summary Table.
Command Data Register 8
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA9 is shown in Figure 6-25 and described in Table 6-35.
Return to the Summary Table.
Command Data Register 9
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA10 is shown in Figure 6-26 and described in Table 6-36.
Return to the Summary Table.
Command Data Register 10
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA11 is shown in Figure 6-27 and described in Table 6-37.
Return to the Summary Table.
Command Data Register 11
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA12 is shown in Figure 6-28 and described in Table 6-38.
Return to the Summary Table.
Command Data Register 12
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA13 is shown in Figure 6-29 and described in Table 6-39.
Return to the Summary Table.
Command Data Register 13
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA14 is shown in Figure 6-30 and described in Table 6-40.
Return to the Summary Table.
Command Data Register 14
This register contains the data for a command.
This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA15 is shown in Figure 6-31 and described in Table 6-41.
Return to the Summary Table.
Command Data Register 15
This register contains the data for a command.
This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA16 is shown in Figure 6-32 and described in Table 6-42.
Return to the Summary Table.
Command Data Register 16
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA17 is shown in Figure 6-33 and described in Table 6-43.
Return to the Summary Table.
Command Data Register 17
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA18 is shown in Figure 6-34 and described in Table 6-44.
Return to the Summary Table.
Command Data Register 18
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA19 is shown in Figure 6-35 and described in Table 6-45.
Return to the Summary Table.
Command Data Register 19
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA20 is shown in Figure 6-36 and described in Table 6-46.
Return to the Summary Table.
Command Data Register 20
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA21 is shown in Figure 6-37 and described in Table 6-47.
Return to the Summary Table.
Command Data Register 21
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA22 is shown in Figure 6-38 and described in Table 6-48.
Return to the Summary Table.
Command Data Register 22
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA23 is shown in Figure 6-39 and described in Table 6-49.
Return to the Summary Table.
Command Data Register 23
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA24 is shown in Figure 6-40 and described in Table 6-50.
Return to the Summary Table.
Command Data Register 24
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA25 is shown in Figure 6-41 and described in Table 6-51.
Return to the Summary Table.
Command Data Register 25
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA26 is shown in Figure 6-42 and described in Table 6-52.
Return to the Summary Table.
Command Data Register 26
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA27 is shown in Figure 6-43 and described in Table 6-53.
Return to the Summary Table.
Command Data Register 27
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA28 is shown in Figure 6-44 and described in Table 6-54.
Return to the Summary Table.
Command Data Register 28
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA29 is shown in Figure 6-45 and described in Table 6-55.
Return to the Summary Table.
Command Data Register 29
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA30 is shown in Figure 6-46 and described in Table 6-56.
Return to the Summary Table.
Command Data Register 30
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATA31 is shown in Figure 6-47 and described in Table 6-57.
Return to the Summary Table.
Command Data Register 31
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDDATAECC0 is shown in Figure 6-48 and described in Table 6-58.
Return to the Summary Table.
Command Data Register 0
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 0.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC1 is shown in Figure 6-49 and described in Table 6-59.
Return to the Summary Table.
Command Data Register 1
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 1.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC2 is shown in Figure 6-50 and described in Table 6-60.
Return to the Summary Table.
Command Data Register 2
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 2.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC3 is shown in Figure 6-51 and described in Table 6-61.
Return to the Summary Table.
Command Data Register 3
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 3.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC4 is shown in Figure 6-52 and described in Table 6-62.
Return to the Summary Table.
Command Data Register 4
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 4.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC5 is shown in Figure 6-53 and described in Table 6-63.
Return to the Summary Table.
Command Data Register 5
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 5.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC6 is shown in Figure 6-54 and described in Table 6-64.
Return to the Summary Table.
Command Data Register 6
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 6.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDDATAECC7 is shown in Figure 6-55 and described in Table 6-65.
Return to the Summary Table.
Command Data Register 7
This register forms the ECC portion of the data for a command. This ECC data in this register covers flash data register 7.
The hardware ECC generation can be overridden and ECC data developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL1 | VAL0 | |||||||||||||||||||||||||||||
R/W-0h | R/W-FFh | R/W-FFh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-8 | VAL1 | R/W | FFh | ECC data for bits 127:64 of the data is placed here.
0h = Minimum value FFh = Maximum value |
7-0 | VAL0 | R/W | FFh | ECC data for bits 63:0 of the data is placed here.
0h = Minimum value FFh = Maximum value |
CMDWEPROTA is shown in Figure 6-56 and described in Table 6-66.
Return to the Summary Table.
Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32 sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Each bit protects 1 sector.
bit [0]: When 1, sector 0 of the flash memory will be protected from program
and erase.
bit [1]: When 1, sector 1 of the flash memory will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the flash memory will be protected from program
and erase.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDWEPROTB is shown in Figure 6-57 and described in Table 6-67.
Return to the Summary Table.
Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present, the first 32 sectors are protected via the CMDWEPROTA register. Thus, the protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first 32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of bit 4 and above would begin at sector 32. Bits 3:0 of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has no effect, so the bits in CMDWEPROTB will protect these banks starting from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors
in the flash will be protected from program and erase. A maximum of 256
sectors can be protected with this register.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDWEPROTC is shown in Figure 6-58 and described in Table 6-68.
Return to the Summary Table.
Command WriteErase Protect C Register
This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors.
This register extends the protection bits from the CMDWEPROTB register to cover bank sizes larger than 32*8=256 sectors. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors
in the flash will be protected from program and erase. Note that the sectors
protected with this register start at sector 256 in the flash, where the sectors
protected by the CMDWEPROTB register end.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CMDWEPROTNM is shown in Figure 6-59 and described in Table 6-69.
Return to the Summary Table.
Command WriteErase Protect Non-Main Register
This register allows non-main region sectors to be protected from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
In addition, this register is used to aggregate
masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all commands.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Each bit protects 1 sector.
bit [0]: When 1, sector 0 of the non-main region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the non-main region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the non-main will be protected from program
and erase.
0h = Minimum value of [VAL] FFFFFFFFh = Maximum value of [VAL] |
CFGPCNT is shown in Figure 6-60 and described in Table 6-70.
Return to the Summary Table.
Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by hardware.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MAXERSPCNTVAL | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MAXERSPCNTVAL | RESERVED | MAXERSPCNTOVR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAXPCNTVAL | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXPCNTVAL | RESERVED | MAXPCNTOVR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | MAXERSPCNTVAL | R/W | 0h | Override maximum pulse count for erase with this value.
If MAXERSPCNTOVR = 0, then this field is ignored.
If MAXERSPCNTOVR = 1, then this value will be used
to override the max pulse count for erase.
0h = Minimum value FFFh = Maximum value |
19-17 | RESERVED | R/W | 0h | Reserved |
16 | MAXERSPCNTOVR | R/W | 0h | Override hard-wired maximum pulse count for erase. If set, then the value
in MAXERSPCNTVAL will be used as the max pulse count for erase operations.
By default, this bit is 0, and a hard-wired max pulse count is used.
0h = Use hard-wired (default) value for maximum pulse count 1h = Use value from MAXERSPCNTVAL field as maximum erase pulse count |
15-12 | RESERVED | R/W | 0h | Reserved |
11-4 | MAXPCNTVAL | R/W | 0h | Override maximum pulse counter with this value.
If MAXPCNTOVR = 0, then this field is ignored.
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used
to override the max pulse count for both program and erase. Full max value
will be {4'h0, MAXPCNTVAL} .
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used
to override the max pulse count for program only. Full max value will be
{4'h0, MAXPCNTVAL}.
0h = Minimum value FFh = Maximum value |
3-1 | RESERVED | R/W | 0h | Reserved |
0 | MAXPCNTOVR | R/W | 0h | Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count
setting for program. By default, this bit is 0, and a hard-wired max pulse count is used. 0h = Use hard-wired (default) value for maximum pulse count 1h = Use value from MAXPCNTVAL field as maximum pulse count |
STATCMD is shown in Figure 6-61 and described in Table 6-71.
Return to the Summary Table.
Command Status Register This register contains status regarding completion and errors of command execution.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FAILMISC | RESERVED | RESERVED | ||||
R-0h | R-0h | R-0h | R- | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAILMODE | FAILILLADDR | FAILVERIFY | FAILWEPROT | RESERVED | CMDINPROGRESS | CMDPASS | CMDDONE |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12 | FAILMISC | R | 0h | Command failed due to error other than write/erase protect violation or verify
error. This is an extra bit in case a new failure mechanism is added which
requires a status bit.
0h = No Fail 1h = Fail |
11-9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | |
7 | FAILMODE | R | 0h | Command failed because a bank has been set to a mode other than READ.
Program and Erase commands cannot be initiated unless all banks are in READ
mode.
0h = No Fail 1h = Fail |
6 | FAILILLADDR | R | 0h | Command failed due to the use of an illegal address
0h = No Fail 1h = Fail |
5 | FAILVERIFY | R | 0h | Command failed due to verify error
0h = No Fail 1h = Fail |
4 | FAILWEPROT | R | 0h | Command failed due to Write/Erase Protect Sector Violation
0h = No Fail 1h = Fail |
3 | RESERVED | R | 0h | Reserved |
2 | CMDINPROGRESS | R | 0h | Command In Progress
0h = Complete 1h = In Progress |
1 | CMDPASS | R | 0h | Command Pass - valid when CMD_DONE field is 1
0h = Fail 1h = Pass |
0 | CMDDONE | R | 0h | Command Done
0h = Not Done 1h = Done |
STATADDR is shown in Figure 6-62 and described in Table 6-72.
Return to the Summary Table.
Current Address Counter Value Read only register giving read access to the state machine current address. A bank id, region id and address are stored in this register and are incremented as necessary during execution of a command.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BANKID | REGIONID | |||||||||||||
R-0h | R-0h | R-1h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BANKADDR | |||||||||||||||
R-0h | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25-21 | BANKID | R | 0h | Current Bank ID
A bank indicator is stored in this register which represents the current bank on
which the state machine is operating. There is 1 bit per bank.
1h (R/W) = Bank 0 2h (R/W) = Bank 1 4h (R/W) = Bank 2 8h (R/W) = Bank 3 10h (R/W) = Bank 4 |
20-16 | REGIONID | R | 1h | Current Region ID
A region indicator is stored in this register which represents the current flash
region on which the state machine is operating.
1h (R/W) = Main Region 2h (R/W) = Non-Main Region 4h (R/W) = Trim Region 8h (R/W) = Engr Region |
15-0 | BANKADDR | R | 0h | Current Bank Address
A bank offset address is stored in this register.
0h = Minimum value FFFFh = Maximum value |
STATPCNT is shown in Figure 6-63 and described in Table 6-73.
Return to the Summary Table.
Current Pulse Count Register: Read only register giving read access to the state machine current pulse count value for program/erase operations.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PULSECNT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-0 | PULSECNT | R | 0h | Current Pulse Counter Value
0h = Minimum value FFFh = Maximum value |