SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

25.3 Timers (TIMx) Registers

Table 25-26 lists the memory-mapped registers for the Timers (TIMx) registers. All register offset addresses not listed in Table 25-26 should be considered as reserved locations and the register contents should not be modified.

Table 25-26 TIMERS (TIMX) Registers
OffsetAcronymRegister NameGroupSection
400hFSUB_0Subsciber Port 0Go
404hFSUB_1Subscriber Port 1Go
444hFPUB_0Publisher Port 0Go
448hFPUB_1Publisher Port 1Go
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1000hCLKDIVClock DividerGo
1008hCLKSELClock Select for Ultra Low Power peripheralsGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt indexGEN_EVENT0Go
1058hIMASKInterrupt maskGEN_EVENT0Go
1060hRISRaw interrupt statusGEN_EVENT0Go
1068hMISMasked interrupt statusGEN_EVENT0Go
1070hISETInterrupt setGEN_EVENT0Go
1078hICLRInterrupt clearGEN_EVENT0Go
1080hIIDXInterrupt indexGEN_EVENT1Go
1088hIMASKInterrupt maskGEN_EVENT1Go
1090hRISRaw interrupt statusGEN_EVENT1Go
1098hMISMasked interrupt statusGEN_EVENT1Go
10A0hISETInterrupt setGEN_EVENT1Go
10A8hICLRInterrupt clearGEN_EVENT1Go
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hCCPDCCP DirectionGo
1104hODISOutput DisableGo
1108hCCLKCTLCounter Clock Control RegisterGo
110ChCPSClock Prescale RegisterGo
1110hCPSVClock prescale count status registerGo
1114hCTTRIGCTLTimer Cross Trigger Control RegisterGo
111ChCTTRIGTimer Cross Trigger RegisterGo
1120hFSCTLFault Source ControlGo
1124hGCTLGlobal control registerGo
1800hCTRCounter RegisterGo
1804hCTRCTLCounter Control RegisterGo
1808hLOADLoad RegisterGo
1810h + formulaCC_01[y]Capture or Compare Register 0/1Go
1818h + formulaCC_23[y]Capture or Compare Register 0/1Go
1820h + formulaCC_45[y]The CC_45 register are a registers which can be used as compare to the current CTR to create an events CC4U, CC4D, CC5U and CC5D.Go
1830h + formulaCCCTL_01[y]Capture or Compare Control RegistersGo
1838h + formulaCCCTL_23[y]Capture or Compare Control Registers 0/1Go
1840h + formulaCCCTL_45[y]Capture or Compare Control Registers 2/3Go
1850h + formulaOCTL_01[y]CCP Output Control Registers 4/5Go
1858h + formulaOCTL_23[y]CCP Output Control Registers 0/1Go
1870h + formulaCCACT_01[y]Capture or Compare Action Registers 2/3Go
1878h + formulaCCACT_23[y]Capture or Compare Action Registers 0/1Go
1880h + formulaIFCTL_01[y]Input Filter Control Register 0/1Go
1888h + formulaIFCTL_23[y]Input Filter Control Register 2/3Go
18A0hPLPhase Load RegisterGo
18A4hDBCTLDead Band insertion control registerGo
18B0hTSELTrigger Select RegisterGo
18B4hRCRepeat counter RegisterGo
18B8hRCLDRepeat counter load RegisterGo
18BChQDIRQEI Count Direction RegisterGo
18D0hFCTLFault Control RegisterGo
18D4hFIFCTLFault input Filter control registerGo

Complex bit access types are encoded to fit into small table cells. Table 25-27 shows the codes that are used for access types in this section.

Table 25-27 Timers (TIMx) Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
KKWrite protected by a key
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

25.3.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 25-41 and described in Table 25-28.

Return to the Summary Table.

Subscriber port

Figure 25-41 FSUB_0
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 25-28 FSUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

25.3.2 FSUB_1 (Offset = 404h) [Reset = 00000000h]

FSUB_1 is shown in Figure 25-42 and described in Table 25-29.

Return to the Summary Table.

Subscriber port

Figure 25-42 FSUB_1
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 25-29 FSUB_1 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

25.3.3 FPUB_0 (Offset = 444h) [Reset = 00000000h]

FPUB_0 is shown in Figure 25-43 and described in Table 25-30.

Return to the Summary Table.

Publisher port

Figure 25-43 FPUB_0
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 25-30 FPUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

25.3.4 FPUB_1 (Offset = 448h) [Reset = 00000000h]

FPUB_1 is shown in Figure 25-44 and described in Table 25-31.

Return to the Summary Table.

Publisher port

Figure 25-44 FPUB_1
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 25-31 FPUB_1 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

25.3.5 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 25-45 and described in Table 25-32.

Return to the Summary Table.

Register to control the power state

Figure 25-45 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hK-0h
Table 25-32 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLEK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

25.3.6 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 25-46 and described in Table 25-33.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 25-46 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 25-33 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

25.3.7 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 25-47 and described in Table 25-34.

Return to the Summary Table.

peripheral enable and reset status

Figure 25-47 STAT
3130292827262524
RESERVED
R-
2322212019181716
RESERVEDRESETSTKY
R-R-0h
15141312111098
RESERVED
R-
76543210
RESERVED
R-
Table 25-34 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

25.3.8 CLKDIV (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 25-48 and described in Table 25-35.

Return to the Summary Table.

This register is used to specify module-specific divide ratio of the functional clock

Figure 25-48 CLKDIV
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDRATIO
R/W-0hR/W-0h
Table 25-35 CLKDIV Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0RATIOR/W0hSelects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

25.3.9 CLKSEL (Offset = 1008h) [Reset = 00000000h]

CLKSEL is shown in Figure 25-49 and described in Table 25-36.

Return to the Summary Table.

Clock Source Select Register

Figure 25-49 CLKSEL
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDBUSCLK_SELMFCLK_SELLFCLK_SELRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 25-36 CLKSEL Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3BUSCLK_SELR/W0hSelects BUSCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
2MFCLK_SELR/W0hSelects MFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
1LFCLK_SELR/W0hSelects LFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
0RESERVEDR/W0h

25.3.10 PDBGCTL (Offset = 1018h) [Reset = 00000003h]

PDBGCTL is shown in Figure 25-50 and described in Table 25-37.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 25-50 PDBGCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDSOFTFREE
R/W-R/W-1hR/W-1h
Table 25-37 PDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

25.3.11 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 25-51 and described in Table 25-38.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 25-51 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 25-38 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

25.3.12 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 25-52 and described in Table 25-39.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”

Figure 25-52 IMASK
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R/W-R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-R/W-0hR/W-0h
Table 25-39 IMASK Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28QEIERRR/W0hQEIERR Event mask
0h = Disable Event
1h = Enable Event
27DCR/W0hDirection Change Event mask
0h = Disable Event
1h = Enable Event
26REPCR/W0hRepeat Counter Zero Event mask
0h = Disable Event
1h = Enable Event
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24FR/W0hFault Event mask
0h = Disable Event
1h = Enable Event
23-16RESERVEDR/W0h
15CCU5R/W0hCompare UP event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14CCU4R/W0hCompare UP event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13CCD5R/W0hCompare DN event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12CCD4R/W0hCompare DN event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11CCU3R/W0hCapture or Compare UP event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10CCU2R/W0hCapture or Compare UP event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7CCD3R/W0hCapture or Compare DN event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6CCD2R/W0hCapture or Compare DN event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

25.3.13 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 25-53 and described in Table 25-40.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 25-53 RIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-40 RIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCU4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCD5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCD4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3

0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2

0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.14 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 25-54 and described in Table 25-41.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 25-54 MIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-41 MIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.15 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 25-55 and described in Table 25-42.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 25-55 ISET
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-42 ISET Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0hQEIERR event SET
0h = Writing 0 has no effect.
1h = Event Set
27DCW0hDirection Change event SET
0h = Writing 0 has no effect.
1h = Event Set
26REPCW0hRepeat Counter Zero event SET
0h = Writing 0 has no effect.
1h = Event Set
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24FW0h Fault event SET
0h = Writing 0 has no effect.
1h = Event Set
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
14CCU4W0hCompare up event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
13CCD5W0hCompare down event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
12CCD4W0hCompare down event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
11CCU3W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
10CCU2W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7CCD3W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
6CCD2W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

25.3.16 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 25-56 and described in Table 25-43.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 25-56 ICLR
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-43 ICLR Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0h QEIERR event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
27DCW0h Direction Change event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
26REPCW0hRepeat Counter Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24FW0h Fault event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
14CCU4W0hCompare up event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
13CCD5W0hCompare down event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
12CCD4W0hCompare down event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
11CCU3W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
10CCU2W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7CCD3W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
6CCD2W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

25.3.17 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 25-57 and described in Table 25-44.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 25-57 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 25-44 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

25.3.18 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 25-58 and described in Table 25-45.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”

Figure 25-58 IMASK
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R/W-R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-R/W-0hR/W-0h
Table 25-45 IMASK Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28QEIERRR/W0hQEIERR Event mask
0h = Disable Event
1h = Enable Event
27DCR/W0hDirection Change Event mask
0h = Disable Event
1h = Enable Event
26REPCR/W0hRepeat Counter Zero Event mask
0h = Disable Event
1h = Enable Event
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24FR/W0hFault Event mask
0h = Disable Event
1h = Enable Event
23-16RESERVEDR/W0h
15CCU5R/W0hCompare UP event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14CCU4R/W0hCompare UP event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13CCD5R/W0hCompare DN event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12CCD4R/W0hCompare DN event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11CCU3R/W0hCapture or Compare UP event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10CCU2R/W0hCapture or Compare UP event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7CCD3R/W0hCapture or Compare DN event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6CCD2R/W0hCapture or Compare DN event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

25.3.19 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 25-59 and described in Table 25-46.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 25-59 RIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-46 RIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCU4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCD5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCD4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3

0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2

0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.20 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 25-60 and described in Table 25-47.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 25-60 MIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-47 MIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.21 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 25-61 and described in Table 25-48.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 25-61 ISET
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-48 ISET Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0hQEIERR event SET
0h = Writing 0 has no effect.
1h = Event Set
27DCW0hDirection Change event SET
0h = Writing 0 has no effect.
1h = Event Set
26REPCW0hRepeat Counter Zero event SET
0h = Writing 0 has no effect.
1h = Event Set
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24FW0h Fault event SET
0h = Writing 0 has no effect.
1h = Event Set
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
14CCU4W0hCompare up event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
13CCD5W0hCompare down event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
12CCD4W0hCompare down event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
11CCU3W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
10CCU2W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7CCD3W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
6CCD2W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

25.3.22 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 25-62 and described in Table 25-49.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 25-62 ICLR
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-49 ICLR Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0h QEIERR event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
27DCW0h Direction Change event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
26REPCW0hRepeat Counter Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24FW0h Fault event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
14CCU4W0hCompare up event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
13CCD5W0hCompare down event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
12CCD4W0hCompare down event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
11CCU3W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
10CCU2W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7CCD3W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
6CCD2W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

25.3.23 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 25-63 and described in Table 25-50.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 25-63 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 25-50 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = Interrupt Source: Zero event (Z)
02h = nterrupt Source: Load event (L)
05h = Interrupt Source: Capture or compare down event (CCD0)
06h = Interrupt Source: Capture or compare down event (CCD1)
07h = Interrupt Source: Capture or compare down event (CCD2)
08h = Interrupt Source: Capture or compare down event (CCD3)
09h = Interrupt Source: Capture or compare up event (CCU0)
0Ah = Interrupt Source: Capture or compare up event (CCU1)
0Bh = Interrupt Source: Capture or compare up event (CCU2)
0Ch = Interrupt Source: Capture or compare up event (CCU3)
0Dh = Interrupt Source: Compare down event (CCD4)
0Eh = Interrupt Source: Compare down event (CCD5)
0Fh = Interrupt Source: Compare down event (CCU4)
10h = Interrupt Source: Compare down event (CCU5)
19h = Interrupt Source: Fault Event generated an interrupt. (F)
1Ah = Interrupt Source: Trigger overflow (TOV)
1Bh = Interrupt Source: Repeat Counter Zero (REPC)
1Ch = Interrupt Source: Direction Change (DC)
1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR)

25.3.24 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 25-64 and described in Table 25-51.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”

Figure 25-64 IMASK
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R/W-R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R/W-
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R/W-0hR/W-0hR/W-0hR/W-0hR/W-R/W-0hR/W-0h
Table 25-51 IMASK Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28QEIERRR/W0hQEIERR Event mask
0h = Disable Event
1h = Enable Event
27DCR/W0hDirection Change Event mask
0h = Disable Event
1h = Enable Event
26REPCR/W0hRepeat Counter Zero Event mask
0h = Disable Event
1h = Enable Event
25TOVR/W0hTrigger Overflow Event mask
0h = Disable Event
1h = Enable Event
24FR/W0hFault Event mask
0h = Disable Event
1h = Enable Event
23-16RESERVEDR/W0h
15CCU5R/W0hCompare UP event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14CCU4R/W0hCompare UP event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13CCD5R/W0hCompare DN event mask CCP5
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12CCD4R/W0hCompare DN event mask CCP4
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11CCU3R/W0hCapture or Compare UP event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10CCU2R/W0hCapture or Compare UP event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9CCU1R/W0hCapture or Compare UP event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8CCU0R/W0hCapture or Compare UP event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7CCD3R/W0hCapture or Compare DN event mask CCP3
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6CCD2R/W0hCapture or Compare DN event mask CCP2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5CCD1R/W0hCapture or Compare DN event mask CCP1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4CCD0R/W0hCapture or Compare DN event mask CCP0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-2RESERVEDR/W0h
1LR/W0hLoad Event mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0ZR/W0hZero Event mask
0h = Disable Event
1h = Enable Event

25.3.25 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 25-65 and described in Table 25-52.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 25-65 RIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-52 RIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCU4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCD5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCD4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3

0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2

0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.26 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 25-66 and described in Table 25-53.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 25-66 MIS
3130292827262524
RESERVEDQEIERRDCREPCTOVF
R-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 25-53 MIS Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28QEIERRR0hQEIERR
0h = Event Cleared
1h = Event Set
27DCR0hDirection Change
0h = Event Cleared
1h = Event Set
26REPCR0hRepeat Counter Zero
0h = Event Cleared
1h = Event Set
25TOVR0h Trigger overflow
0h = Event Cleared
1h = Event Set
24FR0hFault
0h = Event Cleared
1h = Event Set
23-16RESERVEDR0h
15CCU5R0hCompare up event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
14CCU4R0hCompare up event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
13CCD5R0hCompare down event generated an interrupt CCP5
0h = Event Cleared
1h = Event Set
12CCD4R0hCompare down event generated an interrupt CCP4
0h = Event Cleared
1h = Event Set
11CCU3R0h Capture or compare up event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
10CCU2R0h Capture or compare up event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
9CCU1R0h Capture or compare up event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
8CCU0R0h Capture or compare up event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
7CCD3R0h Capture or compare down event generated an interrupt CCP3
0h = Event Cleared
1h = Event Set
6CCD2R0h Capture or compare down event generated an interrupt CCP2
0h = Event Cleared
1h = Event Set
5CCD1R0h Capture or compare down event generated an interrupt CCP1
0h = Event Cleared
1h = Event Set
4CCD0R0h Capture or compare down event generated an interrupt CCP0
0h = Event Cleared
1h = Event Set
3-2RESERVEDR0h
1LR0h Load event generated an interrupt.
0h = Event Cleared
1h = Event Set
0ZR0h Zero event generated an interrupt.
0h = Event Cleared
1h = Event Set

25.3.27 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 25-67 and described in Table 25-54.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 25-67 ISET
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-54 ISET Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0hQEIERR event SET
0h = Writing 0 has no effect.
1h = Event Set
27DCW0hDirection Change event SET
0h = Writing 0 has no effect.
1h = Event Set
26REPCW0hRepeat Counter Zero event SET
0h = Writing 0 has no effect.
1h = Event Set
25TOVW0hTrigger Overflow event SET
0h = Writing 0 has no effect.
1h = Event Set
24FW0h Fault event SET
0h = Writing 0 has no effect.
1h = Event Set
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
14CCU4W0hCompare up event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
13CCD5W0hCompare down event 5 SET
0h = Writing 0 has no effect.
1h = Event Set
12CCD4W0hCompare down event 4 SET
0h = Writing 0 has no effect.
1h = Event Set
11CCU3W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
10CCU2W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
9CCU1W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
8CCU0W0h Capture or compare up event SET
0h = Writing 0 has no effect.
1h = Event Set
7CCD3W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
6CCD2W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
5CCD1W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
4CCD0W0h Capture or compare down event SET
0h = Writing 0 has no effect.
1h = Event Set
3-2RESERVEDW0h
1LW0h Load event SET
0h = Writing 0 has no effect.
1h = Event Set
0ZW0h Zero event SET
0h = Writing 0 has no effect.
1h = Event Set

25.3.28 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 25-68 and described in Table 25-55.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 25-68 ICLR
3130292827262524
RESERVEDQEIERRDCREPCTOVF
W-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
RESERVED
W-0h
15141312111098
CCU5CCU4CCD5CCD4CCU3CCU2CCU1CCU0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
CCD3CCD2CCD1CCD0RESERVEDLZ
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 25-55 ICLR Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDW0h
28QEIERRW0h QEIERR event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
27DCW0h Direction Change event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
26REPCW0hRepeat Counter Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
25TOVW0hTrigger Overflow event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
24FW0h Fault event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
23-16RESERVEDW0h
15CCU5W0hCompare up event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
14CCU4W0hCompare up event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
13CCD5W0hCompare down event 5 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
12CCD4W0hCompare down event 4 CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
11CCU3W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
10CCU2W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
9CCU1W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
8CCU0W0h Capture or compare up event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
7CCD3W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
6CCD2W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
5CCD1W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
4CCD0W0h Capture or compare down event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
3-2RESERVEDW0h
1LW0h Load event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear
0ZW0h Zero event CLEAR
0h = Writing 0 has no effect.
1h = Event Clear

25.3.29 EVT_MODE (Offset = 10E0h) [Reset = 00000029h]

EVT_MODE is shown in Figure 25-69 and described in Table 25-56.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 25-69 EVT_MODE
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDEVT2_CFGEVT1_CFGEVT0_CFG
R/W-0hR-2hR-2hR-1h
Table 25-56 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4EVT2_CFGR2hEvent line mode select for event corresponding to GEN_EVENT1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR2hEvent line mode select for event corresponding to GEN_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0EVT0_CFGR1hEvent line mode select for event corresponding to CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

25.3.30 DESC (Offset = 10FCh) [Reset = 11110000h]

DESC is shown in Figure 25-70 and described in Table 25-57.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 25-70 DESC
31302928272625242322212019181716
MODULEID
R-1111h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-R-R-R-
Table 25-57 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR1111hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
0h = Smallest value
Fh = Highest possible value
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0h = Smallest value
Fh = Highest possible value
7-4MAJREVR0hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

25.3.31 CCPD (Offset = 1100h) [Reset = 00000000h]

CCPD is shown in Figure 25-71 and described in Table 25-58.

Return to the Summary Table.

CCP Direction. Controls whether CCP is used as an input or an output.

Figure 25-71 CCPD
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDC0CCP3C0CCP2C0CCP1C0CCP0
R/W-R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-58 CCPD Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3C0CCP3R/W0hCCP3 direction
0h = Input
1h = Output
2C0CCP2R/W0hCCP2 direction
0h = input
1h = Output
1C0CCP1R/W0hCCP1 direction
0h = Input
1h = Output
0C0CCP0R/W0hCCP0 direction
0h = Input
1h = Output

25.3.32 ODIS (Offset = 1104h) [Reset = 00000000h]

ODIS is shown in Figure 25-72 and described in Table 25-59.

Return to the Summary Table.

The ODIS register output is inverted and then ANDed with the output signal selected by the OCTL register CCPO field (before conditional inversion) to allow software the ability to hold the CCP output low during configuration or shutdown.

Figure 25-72 ODIS
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDC0CCP3C0CCP2C0CCP1C0CCP0
R/W-R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-59 ODIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3C0CCP3R/W0hCounter CCP3 Disable Mask
Defines whether CCP3 of Counter n is forced low or not
0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output is forced low.
2C0CCP2R/W0hCounter CCP2 Disable Mask
Defines whether CCP2 of Counter n is forced low or not
0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output is forced low.
1C0CCP1R/W0hCounter CCP1 Disable Mask
Defines whether CCP0 of Counter n is forced low or not

0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output is forced low.
0C0CCP0R/W0hCounter CCP0 Disable Mask
Defines whether CCP0 of Counter n is forced low or not

0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block.
1h = CCP output is forced low.

25.3.33 CCLKCTL (Offset = 1108h) [Reset = 00000000h]

CCLKCTL is shown in Figure 25-73 and described in Table 25-60.

Return to the Summary Table.

The CCLKCTL register provides a SW mechanism for gating the TIMER clock
if the module is expected not to be used but the power domain is alive.
This effectively puts the IP in an IDLE state

Figure 25-73 CCLKCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDCLKEN
R/W-R/W-0h
Table 25-60 CCLKCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0CLKENR/W0hClock Enable
Disables the clock gating to the module. SW has to explicitly program the value
to 0 to gate the clock.

0h = Clock is disabled.
1h = Clock is enabled

25.3.34 CPS (Offset = 110Ch) [Reset = 00000000h]

CPS is shown in Figure 25-74 and described in Table 25-61.

Return to the Summary Table.

The CPS register provides the value for the clock pre-scaler.

Figure 25-74 CPS
313029282726252423222120191817161514131211109876543210
RESERVEDPCNT
R/W-R/W-0h
Table 25-61 CPS Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0PCNTR/W0hPre-Scale Count
This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1).
A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider.
A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock

0h = Minimum value

FFh = Maximum Value

25.3.35 CPSV (Offset = 1110h) [Reset = 00000000h]

CPSV is shown in Figure 25-75 and described in Table 25-62.

Return to the Summary Table.

The CPSV register provides the ability to read the current clock prescale count value.

Figure 25-75 CPSV
313029282726252423222120191817161514131211109876543210
RESERVEDCPSVAL
R-R-0h
Table 25-62 CPSV Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0CPSVALR0hCurrent Prescale Count Value
0h = Minimum value

FFh = Maximum Value

25.3.36 CTTRIGCTL (Offset = 1114h) [Reset = 00000000h]

CTTRIGCTL is shown in Figure 25-76 and described in Table 25-63.

Return to the Summary Table.

Cross Timer Trigger Control Register
This register is used to control the cross trigger connections for enables and faults of different timer instances in the same power domain. Please refer to sections Timer Module Cross Trigger (In/Out) and Fault Cross Triggering for details.

Figure 25-76 CTTRIGCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVEDEVTCTTRIGSEL
R/W-R/W-0h
15141312111098
RESERVED
R/W-
76543210
RESERVEDEVTCTENCTEN
R/W-R/W-0hR/W-0h
Table 25-63 CTTRIGCTL Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16EVTCTTRIGSELR/W0hUsed to Select the subscriber port that should be used for input cross trigger.
0h = Use FSUB0 as cross trigger source.
1h = Use FSUB1 as cross trigger source.
2h = Use Zero event as cross trigger source.
3h = Use Load event as cross trigger source.
4h = Use CCD0 event as cross trigger source.
5h = Use CCD1 event as cross trigger source.
6h = Use CCD2 event as cross trigger source.
7h = Use CCD3 event as cross trigger source.
8h = Use CCU0 event as cross trigger source.
9h = Use CCU1 event as cross trigger source.
Ah = Use CCU2 event as cross trigger source.
Bh = Use CCU3 event as cross trigger source.
15-2RESERVEDR/W0h
1EVTCTENR/W0hEnable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers.
0h = Cross trigger generation disabled.
1h = Cross trigger generation enabled
0CTENR/W0hTimer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system.
These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain.

The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.
0h = Cross trigger generation disabled.
1h = Cross trigger generation enabled

25.3.37 CTTRIG (Offset = 111Ch) [Reset = 00000000h]

CTTRIG is shown in Figure 25-77 and described in Table 25-64.

Return to the Summary Table.

Cross Timer Trigger Register
This register is used to trigger the timer instances connected and enabled using CTTRIGCTL and CTTRIGMSK registers.

Figure 25-77 CTTRIG
3130292827262524
RESERVED
W-
2322212019181716
RESERVED
W-
15141312111098
RESERVED
W-
76543210
RESERVEDTRIG
W-W-0h
Table 25-64 CTTRIG Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0TRIGW0hGenerate Cross Trigger
This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.

0h = Cross trigger generation disabled
1h = Generate Cross trigger pulse

25.3.38 FSCTL (Offset = 1120h) [Reset = 00000000h]

FSCTL is shown in Figure 25-78 and described in Table 25-65.

Return to the Summary Table.

The FSCTL register controls the fault source selection and enable. There are 5 input fault sources either through synchronous path processing or asynchronous path.

Figure 25-78 FSCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDFEX2ENFEX1ENFEX0ENFAC2ENFAC1ENFAC0ENFCEN
R/W-R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 25-65 FSCTL Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0h
6FEX2ENR/W0hThis field controls whether the fault is caused by external fault pin 2.
0h = Disable

1h = Enable


5FEX1ENR/W0hThis field controls whether the fault is caused by external fault pin 1.
0h = Disable

1h = Enable


4FEX0ENR/W0hThis field controls whether the fault is caused by external fault pin 0.
0h = Disable

1h = Enable


3FAC2ENR/W0hThis field controls whether the fault is caused by COMP2 output.
0h = Disable

1h = Enable


2FAC1ENR/W0hThis field controls whether the fault is caused by COMP1 output.
0h = Disable

1h = Enable


1FAC0ENR/W0hThis field controls whether the fault signal is caused by COMP0 output.
0h = Disable

1h = Enable


0FCENR/W0hThis field controls whether the fault is caused by the system clock fault.
0h = Disable

1h = Enable


25.3.39 GCTL (Offset = 1124h) [Reset = 00000001h]

GCTL is shown in Figure 25-79 and described in Table 25-66.

Return to the Summary Table.

Global control register

Figure 25-79 GCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDSHDWLDEN
R/W-R/W-1h
Table 25-66 GCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0SHDWLDENR/W1hEnables shadow to active load of bufferred registers and register fields.
0h = Disable

1h = Enable


25.3.40 CTR (Offset = 1800h) [Reset = 00000000h]

CTR is shown in Figure 25-80 and described in Table 25-67.

Return to the Summary Table.

This is the TIMER counter register.
This can be set by SW. However, the writes will be unpredictable if the software
tries to set a value while the counter is running.

Figure 25-80 CTR
313029282726252423222120191817161514131211109876543210
RESERVEDCCTR
R/W-0hR/W-0h
Table 25-67 CTR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCTRR/W0h Current Counter value
0h = Minimum value

00FFFFFFh = Maximum Value

25.3.41 CTRCTL (Offset = 1804h) [Reset = 0000FF80h]

CTRCTL is shown in Figure 25-81 and described in Table 25-68.

Return to the Summary Table.

This register provides control over the counter operation.
The configuration can change as well as setting the EN bit in a single write.
There is no requirement to change the configuration first and then do an
additional write to set the EN bit.

Figure 25-81 CTRCTL
3130292827262524
RESERVEDCVAERESERVEDPLEN
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
SLZERCNEZRESERVEDFRBFBDRBRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CZCCACCLC
R/W-7hR/W-7hR/W-7h
76543210
CLCRESERVEDCMREPEATEN
R/W-7hR/W-0hR/W-0hR/W-0hR/W-0h
Table 25-68 CTRCTL Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29-28CVAER/W0h Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0h = The counter is set to the LOAD register value
1h = The counter value is unchanged from its current value which could have been initialized by software
2h = The counter is set to zero
27-25RESERVEDR/W0h
24PLENR/W0h Phase Load Enable. This bit allows the timer to have phase load feature.

0h = Disabled
1h = Enabled
23SLZERCNEZR/W0hSuppress Load and Zero Events if Repeat Counter is Not Equal to Zero.
This bit suppresses the generation of the Z (zero)
and L (load) events from the counter when the
repeat counter (RC) value is not 0.
0h = Disabled. Z and L events are always generated from the counter when their conditions are generated.
1h = Enabled. Z and L events are generated from the counter when their conditions are generated and the RC register value is 0.
22-20RESERVEDR/W0h
19FRBR/W0h Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition.
0h = Resume counting
1h = Perform the action as specified by the CVAE field.
18FBR/W0h Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0
0h = Continues counting
1h = Suspends counting
17DRBR/W0h Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0h = Resume counting
1h = Perform the action as specified by the CVAE field.
16RESERVEDR/W0h
15-13CZCR/W7h Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value.

Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 ZCOND
1h = CCCTL_1 ZCOND
2h = CCCTL_2 ZCOND
This value exists when there are 4 channels.
3h = CCCTL_3 ZCOND
This value exists when there are 4 channels.
4h = Controlled by 2-input QEI mode

This value exists when TIMER support QEI feature.
5h = Controlled by 3-input QEI mode

This value exists when TIMER support QEI feature.
12-10CACR/W7h Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value.
Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 ACOND
1h = CCCTL_1 ACOND
2h = CCCTL_2 ACOND
This value exists when there are 4 channels.
3h = CCCTL_3 ACOND
This value exists when there are 4 channels.
4h = Controlled by 2-input QEI mode

This value exists when TIMER support QEI feature.
5h = Controlled by 3-input QEI mode

This value exists when TIMER support QEI feature.
9-7CLCR/W7h Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value.

Encodings 1-3 are present based on the CCPC
parameter value. Bits 4-5 are present based on
the HQEI parameter value. Any encodings not
provided are documented as reserved.
0h = CCCTL_0 LCOND
1h = CCCTL_1 LCOND
2h = CCCTL_2 LCOND
This value exists when there are 4 channels.
3h = CCCTL_3 LCOND
This value exists when there are 4 channels.
4h = Controlled by 2 input QEI mode.
This value exists when TIMER support QEI feature.
5h = Controlled by 3 input QEI mode.

This value exists when TIMER support QEI feature.
6RESERVEDR/W0h
5-4CMR/W0h Count Mode
0h = Down
1h = Up/Down
2h = Counter counts up.
3-1REPEATR/W0h Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0h = Does not automatically advance following a zero event.
1h = Continues to advance following a zero event.
2h = Reserved
3h = Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode.
4h = Reserved
0ENR/W0h Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0h = Disabled
1h = Enabled

25.3.42 LOAD (Offset = 1808h) [Reset = 00000000h]

LOAD is shown in Figure 25-82 and described in Table 25-69.

Return to the Summary Table.

The contents of LOAD register are copied to CTR on any operation designated to do a "LOAD". The LOAD is used to compare with the CTR for generating a "Load Event" that can be used for interrupt, trigger, or signal generator actions.

Figure 25-82 LOAD
313029282726252423222120191817161514131211109876543210
RESERVEDLD
R/W-0hR/W-0h
Table 25-69 LOAD Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0LDR/W0h Load Value
0h = Minimum value

00FFFFFFh = Maximum Value

25.3.43 CC_01[y] (Offset = 1810h + formula) [Reset = 00000000h]

CC_01[y] is shown in Figure 25-83 and described in Table 25-70.

Return to the Summary Table.

The CC_01 register is a register that can be used as either a capture register, to capture the next CTR value on an event, or a compare to the current CTR to create an event. It cannot operate concurrently as both. There are two Capture-Compare slices of hardware for each counter, hence there are two CC_01 registers per timer. On a capture event, the next value of the CTR is loaded so that CTR and CC_01 (which captured) will be equal on the cycle that an interrupt or trigger is created from the capture action.

Offset = 1810h + (y * 4h); where y = 0h to 1h

Figure 25-83 CC_01[y]
313029282726252423222120191817161514131211109876543210
RESERVEDCCVAL
R/W-0hR/W-0h
Table 25-70 CC_01[y] Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCVALR/W0h Capture or compare value
0h = Minimum value

FFFFh = Maximum Value

25.3.44 CC_23[y] (Offset = 1818h + formula) [Reset = 00000000h]

CC_23[y] is shown in Figure 25-84 and described in Table 25-71.

Return to the Summary Table.

The CC_23 register is a register that can be used as either a capture register, to capture the next CTR value on an event, or a compare to the current CTR to create an event. It cannot operate concurrently as both. There are two Capture-Compare slices of hardware for each counter, hence there are two CC_01 registers per timer. On a capture event, the next value of the CTR is loaded so that CTR and CC_01 (which captured) will be equal on the cycle that an interrupt or trigger is created from the capture action.

Offset = 1818h + (y * 4h); where y = 0h to 1h

Figure 25-84 CC_23[y]
313029282726252423222120191817161514131211109876543210
RESERVEDCCVAL
R/W-0hR/W-0h
Table 25-71 CC_23[y] Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCVALR/W0h Capture or compare value
0h = Minimum value

FFFFh = Maximum Value

25.3.45 CC_45[y] (Offset = 1820h + formula) [Reset = 00000000h]

CC_45[y] is shown in Figure 25-85 and described in Table 25-72.

Return to the Summary Table.

The CC_45 register are a registers which can be used as compare to the current CTR to create an events CC4U, CC4D, CC5U and CC5D.

Offset = 1820h + (y * 4h); where y = 0h to 1h

Figure 25-85 CC_45[y]
313029282726252423222120191817161514131211109876543210
RESERVEDCCVAL
R/W-0hR/W-0h
Table 25-72 CC_45[y] Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0CCVALR/W0h Capture or compare value
0h = Minimum value

FFFFh = Maximum Value

25.3.46 CCCTL_01[y] (Offset = 1830h + formula) [Reset = 00000000h]

CCCTL_01[y] is shown in Figure 25-86 and described in Table 25-73.

Return to the Summary Table.

The CCCTL_01 registers control the operations of the respective CC registers and the counter.

Offset = 1830h + (y * 4h); where y = 0h to 1h

Figure 25-86 CCCTL_01[y]
3130292827262524
CC2SELDCCACTUPDSCERCNEZCC2SELU
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CC2SELURESERVEDCCUPDCOCRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDZCONDRESERVEDLCOND
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDACONDRESERVEDCCOND
R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-73 CCCTL_01[y] Field Descriptions
BitFieldTypeResetDescription
31-29CC2SELDR/W0hSelects the source second CCD event.
0h = Selects CCD from CC0.
1h = Selects CCD from CC1.
2h = Selects CCD from CC2.
3h = Selects CCD from CC3.
4h = Selects CCD from CC4.
5h = Selects CCD from CC5.
28-26CCACTUPDR/W0hCCACT shadow register Update Method
This field controls how updates to the CCACT shadow register are performed

0h = Value written to the CCACT register has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCACTx_y register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=CC_xy)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero event (CTR=0) or load event (CTR = LOAD)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LDn.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = On a TRIG pulse, the value stored in CCACT_xy shadow register is loaded into CCACT_xy register.
25SCERCNEZR/W0hSuppress Compare Event if Repeat Counter is Not Equal to Zero
This bit suppresses the generation of the compare (CCD, CCU and RC) events from
the counter when the repeat counter (RC) value is not 0.
0h = CCD, CCU and
RC events are always generated
from the counter when their
conditions are generated.
1h = CCD, CCU and
RC events are generated from the
counter when their conditions are
generated and the RC
register value is 0.
24-22CC2SELUR/W0hSelects the source second CCU event.
0h = Selects CCU from CC0.
1h = Selects CCU from CC1.
2h = Selects CCU from CC2.
3h = Selects CCU from CC3.
4h = Selects CCU from CC4.
5h = Selects CCU from CC5.
21RESERVEDR/W0h
20-18CCUPDR/W0hCapture and Compare Update Method
This field controls how updates to the shadow
capture and compare register are performed
(when operating in compare mode, COC=0).
0h = Writes to the CCx_y register is written to the register directly and has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCx_y register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=CC_xy)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero event(CTR=0) or load event (CTR=LOAD)
Writes to the CCx_y
register are stored in
shadow register and transferred to
ECCx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LD.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = Following a TRIG pulse.

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y
17COCR/W0h Capture or Compare.
Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0h = Compare
1h = Capture
16-15RESERVEDR/W0h
14-12ZCONDR/W0h Zero Condition.
This field specifies the condition that generates a zero pulse.
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
11RESERVEDR/W0h
10-8LCONDR/W0h Load Condition.
Specifies the condition that generates a load pulse.
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
7RESERVEDR/W0h
6-4ACONDR/W0h Advance Condition.
Specifies the condition that generates an advance pulse.
0h = Each TIMCLK
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
5h = CCP High or Trigger assertion (level)
3RESERVEDR/W0h
2-0CCONDR/W0h Capture Condition.
Specifies the condition that generates a capture pulse.
0h = None (never captures)
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)

25.3.47 CCCTL_23[y] (Offset = 1838h + formula) [Reset = 00000000h]

CCCTL_23[y] is shown in Figure 25-87 and described in Table 25-74.

Return to the Summary Table.

The CCCTL registers control the operations of the respective CC registers and the counter.

Offset = 1838h + (y * 4h); where y = 0h to 1h

Figure 25-87 CCCTL_23[y]
3130292827262524
CC2SELDCCACTUPDSCERCNEZCC2SELU
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CC2SELURESERVEDCCUPDCOCRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDZCONDRESERVEDLCOND
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDACONDRESERVEDCCOND
R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-74 CCCTL_23[y] Field Descriptions
BitFieldTypeResetDescription
31-29CC2SELDR/W0hSelects the source second CCD event.
0h = Selects CCD from CC0.
1h = Selects CCD from CC1.
2h = Selects CCD from CC2.
3h = Selects CCD from CC3.
4h = Selects CCD from CC4.
5h = Selects CCD from CC5.
28-26CCACTUPDR/W0hCCACT shadow register Update Method
This field controls how updates to the CCCACT shadow register are performed

0h = Value written to the CCACTx_y register has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCACTx_y register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=cc_xy)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero event (CTR=0) or load event (CTR=LOAD)
Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LDn.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCACTx_y
register are stored in
shadow register and transferred to
CCACTx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register.
25SCERCNEZR/W0hSuppress Compare Event if Repeat Counter is Not Equal to Zero
This bit suppresses the generation of the compare (CCD, CCU and RC) events from
the counter when the repeat counter (RCn) value is not 0.
0h = CCD, CCU and
RC events are always generated
from the counter when their
conditions are generated.
1h = CCD, CCU and
RC events are generated from the
counter when their conditions are
generated and the RC
register value is 0.
24-22CC2SELUR/W0hSelects the source second CCU event.
0h = Selects CCU from CC0.
1h = Selects CCU from CC1.
2h = Selects CCU from CC2.
3h = Selects CCU from CC3.
4h = Selects CCU from CC4.
5h = Selects CCU from CC5.
21RESERVEDR/W0h
20-18CCUPDR/W0hCapture and Compare Update Method
This field controls how updates to the shadow
capture and compare register are performed
(when operating in compare mode, COC=0).
0h = Writes to the CCx_y register is written to the register directly and has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCx_y register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=CC_xy)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero or load event
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LDn.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = Following a TRIG pulse.

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y #xD; 0.
17COCR/W0h Capture or Compare.
Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).
0h = Compare
1h = Capture
16-15RESERVEDR/W0h
14-12ZCONDR/W0h Zero Condition.
This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
11RESERVEDR/W0h
10-8LCONDR/W0h Load Condition.
Specifies the condition that generates a load pulse. 4h-Fh = Reserved
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
7RESERVEDR/W0h
6-4ACONDR/W0h Advance Condition.
Specifies the condition that generates an advance pulse. 6h-Fh = Reserved
0h = Each TIMCLK
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)
5h = CCP High or Trigger assertion (level)
3RESERVEDR/W0h
2-0CCONDR/W0h Capture Condition.
Specifies the condition that generates a capture pulse. 4h-Fh = Reserved
0h = None (never captures)
1h = Rising edge of CCP or trigger assertion edge
2h = Falling edge of CCP or trigger de-assertion edge
3h = Either edge of CCP or trigger change (assertion/de-assertion edge)

25.3.48 CCCTL_45[y] (Offset = 1840h + formula) [Reset = 00000000h]

CCCTL_45[y] is shown in Figure 25-88 and described in Table 25-75.

Return to the Summary Table.

The CCCTL registers control the operations of the respective CC registers and the counter.

Offset = 1840h + (y * 4h); where y = 0h to 1h

Figure 25-88 CCCTL_45[y]
3130292827262524
RESERVEDSCERCNEZRESERVED
R/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDCCUPDRESERVED
R/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 25-75 CCCTL_45[y] Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0h
25SCERCNEZR/W0hSuppress Compare Event if Repeat Counter is Not Equal to Zero
This bit suppresses the generation of the compare (CCD, CCU and RC) events from
the counter when the repeat counter (RC) value is not 0.
0h = CCD, CCU and
RC events are always generated
from the counter when their
conditions are generated.
1h = CCD, CCU and
RC events are generated from the
counter when their conditions are
generated and the RC
register value is 0.
24-21RESERVEDR/W0h
20-18CCUPDR/W0hCapture and Compare Update Method
This field controls how updates to the shadow
capture and compare register are performed
(when operating in compare mode, COC=0).
0h = Writes to the CCx_y register is written to the register directly and has immediate effect.
1h = Following a zero event (CTR=0)
Writes to the CCx_y
register are stored in
shadow register and transferred to
ECCx_y in the TIMCLK
cycle following CTR
equals 0.
2h = Following a CCD event (CTR=CC_xy)
Writes to the CCx_y register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register value.
3h = Following a CCU event (CTR=CC_xy)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals the CCx_y register
value.
4h = Following a zero event (CTR=0) or load event (CTR=LOAD)
Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0 or CTR. Equals
LD.

Note this update mechanism is
defined for use only in
configurations using up/down
counting. This mode is not intended for use in down count
configurations.
5h = Following a zero event (CTR=0) with repeat count also zero (RC=0).

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y in the TIMCLK
cycle following CTR
equals 0 and if RC equal
0.
6h = Following a TRIG pulse.

Writes to the CCx_y
register are stored in
shadow register and transferred to
CCx_y #xD; 0.
17-0RESERVEDR/W0h

25.3.49 OCTL_01[y] (Offset = 1850h + formula) [Reset = 00000000h]

OCTL_01[y] is shown in Figure 25-89 and described in Table 25-76.

Return to the Summary Table.

The OCTL_01 register controls the CCP output of the Capture-Compare slice of the counter. This includes the ability to select the source of what is driven out along with initial condition values and final inversion options.

Offset = 1850h + (y * 4h); where y = 0h to 1h

Figure 25-89 OCTL_01[y]
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCCPIVCCPOINVCCPO
R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-76 OCTL_01[y] Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5CCPIVR/W0h CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0h = Low
1h = High
4CCPOINVR/W0h CCP Output Invert The output as selected by CCPO is conditionally inverted.
0h = No inversion
1h = Invert
3-0CCPOR/W0h CCP Output Source
0h = Signal generator value (for example, PWM, triggered PWM)
1h = Load event
2h = CCU event or CCD event
4h = Zero event
5h = Capture event
6h = Fault condition
8h = Mirror CCP of first capture and compare register to other capture compare blocks
9h = Mirror CCP of second capture and compare register in other capture compare blocks
Ch = Signal generator output after deadband insertion
Dh = Counter direction

25.3.50 OCTL_23[y] (Offset = 1858h + formula) [Reset = 00000000h]

OCTL_23[y] is shown in Figure 25-90 and described in Table 25-77.

Return to the Summary Table.

The OCTL register controls the CCP output of the Capture-Compare slice of the counter. This includes the ability to select the source of what is driven out along with initial condition values and final inversion options.

Offset = 1858h + (y * 4h); where y = 0h to 1h

Figure 25-90 OCTL_23[y]
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCCPIVCCPOINVCCPO
R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-77 OCTL_23[y] Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5CCPIVR/W0h CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0h = Low
1h = High
4CCPOINVR/W0h CCP Output Invert The output as selected by CCPO is conditionally inverted.
0h = No inversion
1h = Invert
3-0CCPOR/W0h CCP Output Source
0h = Signal generator value (for example, PWM, triggered PWM)
1h = Load condition
2h = CCU event or CCD event
4h = Zero event
5h = Capture event
6h = Fault Condition
8h = Mirror CCP of first capture and compare register in other capture compare blocks
9h = Mirror CCP of second capture and compare register in other capture compare blocksi /bn,.
Ch = Deadband Inserted Output
Dh = Counter direction

25.3.51 CCACT_01[y] (Offset = 1870h + formula) [Reset = 00000000h]

CCACT_01[y] is shown in Figure 25-91 and described in Table 25-78.

Return to the Summary Table.

The CCACT_01 register controls the actions of the signal generator of the capture-compare slice based on the events created in the counter block, the capture and compare block and debug events.

Offset = 1870h + (y * 4h); where y = 0h to 1h

Figure 25-91 CCACT_01[y]
3130292827262524
SWFRCACT_CMPLSWFRCACTFEXACTFENACT
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FENACTRESERVEDCC2UACT
R/W-0hR/W-0hR/W-0h
15141312111098
CC2UACTRESERVEDCC2DACTRESERVEDCUACTRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CDACTRESERVEDLACTRESERVEDZACT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 25-78 CCACT_01[y] Field Descriptions
BitFieldTypeResetDescription
31-30SWFRCACT_CMPLR/W0hCCP Complimentary output Action on Software Force Output

This field describes the resulting action of software force.

This action has a shadow register, which will be updated under specific condition.
So that this register cannot take into effect immediately.


0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP Complimentary output value is set high
2h = CCP Complimentary output value is set low
29-28SWFRCACTR/W0hCCP Output Action on Software Force Output

This field describes the resulting action of software force.

This action has a shadow register, which will be updated under specific condition.
So that this register cannot take into effect immediately.


0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
27-25FEXACTR/W0hCCP Output Action on Fault Exit
This field describes the resulting action of the signal generator upon exiting the fault condition.

0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
4h = CCP output value is tristated
24-22FENACTR/W0hCCP Output Action on Fault Entry
This field describes the resulting action of the signal generator upon detecting a fault.

0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
4h = CCP output value is tristated
21-17RESERVEDR/W0h
16-15CC2UACTR/W0h CCP Output Action on CC2U event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
14RESERVEDR/W0h
13-12CC2DACTR/W0h CCP Output Action on CC2D event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
11RESERVEDR/W0h
10-9CUACTR/W0h CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
8RESERVEDR/W0h
7-6CDACTR/W0h CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
5RESERVEDR/W0h
4-3LACTR/W0h CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
2RESERVEDR/W0h
1-0ZACTR/W0h CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled

25.3.52 CCACT_23[y] (Offset = 1878h + formula) [Reset = 00000000h]

CCACT_23[y] is shown in Figure 25-92 and described in Table 25-79.

Return to the Summary Table.

The CCACT register controls the actions of the signal generator of the capture-compare slice based on the events created in the counter block, the capture and compare block and debug events.

Offset = 1878h + (y * 4h); where y = 0h to 1h

Figure 25-92 CCACT_23[y]
3130292827262524
SWFRCACT_CMPLSWFRCACTFEXACTFENACT
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
FENACTRESERVEDCC2UACT
R/W-0hR/W-0hR/W-0h
15141312111098
CC2UACTRESERVEDCC2DACTRESERVEDCUACTRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CDACTRESERVEDLACTRESERVEDZACT
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 25-79 CCACT_23[y] Field Descriptions
BitFieldTypeResetDescription
31-30SWFRCACT_CMPLR/W0hCCP Complimentary Output Action on Software Force Output

This field describes the resulting action of software force.

This action has a shadow register, which will be updated under specific condition.
So that this register cannot take into effect immediately.


0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP Complimentary output value is set high
2h = CCP Complimentary output value is set low
29-28SWFRCACTR/W0hCCP Output Action on Software Force Output

This field describes the resulting action of software force.

This action has a shadow register, which will be updated under specific condition.
So that this register cannot take into effect immediately.


0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
27-25FEXACTR/W0hCCP Output Action on Fault Exit
This field describes the resulting action of the signal generator upon exiting the fault condition.

0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
4h = CCP output value is tristated
24-22FENACTR/W0hCCP Output Action on Fault Entry
This field describes the resulting action of the signal generator upon detecting a fault.

0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
4h = CCP output value is tristated
21-17RESERVEDR/W0h
16-15CC2UACTR/W0h CCP Output Action on CC2U event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
14RESERVEDR/W0h
13-12CC2DACTR/W0h CCP Output Action on CC2D event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
11RESERVEDR/W0h
10-9CUACTR/W0h CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
8RESERVEDR/W0h
7-6CDACTR/W0h CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
5RESERVEDR/W0h
4-3LACTR/W0h CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled
2RESERVEDR/W0h
1-0ZACTR/W0h CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event.
1h = CCP output value is set high
2h = CCP output value is set low
3h = CCP output value is toggled

25.3.53 IFCTL_01[y] (Offset = 1880h + formula) [Reset = 00000000h]

IFCTL_01[y] is shown in Figure 25-93 and described in Table 25-80.

Return to the Summary Table.

The IFCTL_01 register controls the input selection and inversion for the associated Capture-Compare slice.

Offset = 1880h + (y * 4h); where y = 0h to 1h

Figure 25-93 IFCTL_01[y]
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDFECPVRESERVEDFP
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
INVRESERVEDISEL
R/W-0hR/W-0hR/W-0h
Table 25-80 IFCTL_01[y] Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR/W0h
12FER/W0hFilter Enable
This bit controls whether the input is filtered by
the input filter or bypasses to the edge
detect.
0h = Bypass.
1h = Filtered.
11CPVR/W0hConsecutive Period/Voting Select

This bit controls whether the input filter uses a
stricter consecutive period count or majority
voting.
0h = Consecutive Periods
The input must be at a specific logic level for the period defined by FP before it is passed to the filter output.
1h = Voting

The filter ignores one clock of
opposite logic over the filter
period.
I.e. Over FP samples of the
input, up to 1 sample may be of
an opposite logic value (glitch)
without affecting the output.
10RESERVEDR/W0h
9-8FPR/W0hFilter Period. This field specifies the sample period for the
input filter. I.e. The input is sampled for FP
timer clocks during filtering.
0h = The division factor is 3
1h = The division factor is 5
2h = The division factor is 8
7INVR/W0h Input Inversion This bit controls whether the selected input is inverted.
0h = Noninverted
1h = Inverted
6-4RESERVEDR/W0h
3-0ISELR/W0h Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0h = CCP of the corresponding capture compare unit
1h = Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0.
2h = CCP0 of the counter
3h = Trigger
4h = XOR of CCP inputs as input source (Used in Hall input mode).
5h = subscriber 0 event as input source.
6h = subscriber 1 event as input source.
7h = Comparator 0 output.
8h = Comparator 1 output.
9h = Comparator 2 output.

25.3.54 IFCTL_23[y] (Offset = 1888h + formula) [Reset = 00000000h]

IFCTL_23[y] is shown in Figure 25-94 and described in Table 25-81.

Return to the Summary Table.

The IFCTL register controls the input selection and inversion for the associated Capture-Compare slice.

Offset = 1888h + (y * 4h); where y = 0h to 1h

Figure 25-94 IFCTL_23[y]
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDFECPVRESERVEDFP
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
INVRESERVEDISEL
R/W-0hR/W-0hR/W-0h
Table 25-81 IFCTL_23[y] Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR/W0h
12FER/W0hFilter Enable
This bit controls whether the input is filtered by
the input filter or bypasses to the edge
detect.
0h = Bypass.
1h = Filtered.
11CPVR/W0hConsecutive Period/Voting Select

This bit controls whether the input filter uses a
stricter consecutive period count or majority
voting.
0h = Consecutive Periods
The input must be at a specific logic level for the period defined by FP before it is passed to the filter output.
1h = Voting

The filter ignores one clock of
opposite logic over the filter
period.
I.e. Over FP samples of the
input, up to 1 sample may be of
an opposite logic value (glitch)
without affecting the output.
10RESERVEDR/W0h
9-8FPR/W0hFilter Period. This field specifies the sample period for the
input filter. I.e. The input is sampled for FP
timer clocks during filtering.
0h = The division factor is 3
1h = The division factor is 5
2h = The division factor is 8
7INVR/W0h Input Inversion This bit controls whether the selected input is inverted.
0h = Noninverted
1h = Inverted
6-4RESERVEDR/W0h
3-0ISELR/W0h Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0h = CCP of the corresponding capture compare unit
1h = Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0.
2h = CCP0 of the counter
3h = Trigger
4h = XOR of CCP inputs as input source (Used in Hall input mode).
5h = subscriber 0 event as input source.
6h = subscriber 1 event as input source.
7h = Comparator 0 output.
8h = Comparator 1 output.
9h = Comparator 2 output.

25.3.55 PL (Offset = 18A0h) [Reset = 00000000h]

PL is shown in Figure 25-95 and described in Table 25-82.

Return to the Summary Table.

This is the phase load register.

Figure 25-95 PL
313029282726252423222120191817161514131211109876543210
RESERVEDPHASE
R/W-0hR/W-0h
Table 25-82 PL Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0PHASER/W0hPhase Load value
0h = Minimum value

00FFFFFFh = Maximum Value

25.3.56 DBCTL (Offset = 18A4h) [Reset = 00000000h]

DBCTL is shown in Figure 25-96 and described in Table 25-83.

Return to the Summary Table.

The DBCTL register controls the dead band insertion of the pulse width modulated output.

Figure 25-96 DBCTL
3130292827262524
RESERVEDFALLDELAY
R/W-R/W-0h
2322212019181716
FALLDELAY
R/W-0h
15141312111098
RESERVEDM1_ENABLERISEDELAY
R/W-R/W-R/W-0h
76543210
RISEDELAY
R/W-0h
Table 25-83 DBCTL Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/W0h
27-16FALLDELAYR/W0hFall Delay
The number of TIMCLK periods inserted between the fall edge of CCP signal and the rise edge of CCP complimentary signal.

0h = Minimum value

FFFh = Maximum Value
15-13RESERVEDR/W0h
12M1_ENABLER/W0h Dead Band Mode 1 Enable.
0h = Disabled
1h = Enabled
11-0RISEDELAYR/W0hRise Delay
The number of TIMCLK periods inserted between the falling edge of CCP signal and the rising edge of CCP complimentary signal.

0h = Minimum value

FFFh = Maximum Value

25.3.57 TSEL (Offset = 18B0h) [Reset = 00000000h]

TSEL is shown in Figure 25-97 and described in Table 25-84.

Return to the Summary Table.

The TSEL register controls the input trigger enable and selection of the trigger source. Trigger sources are generated by other peripherals through their respective publisher ports (subscribed in by the timer's subscriber port).

Figure 25-97 TSEL
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDTERESERVEDETSEL
R/W-0hR/W-0hR/W-0hR/W-0h
Table 25-84 TSEL Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9TER/W0hTrigger Enable.
This selects whether a trigger is enabled or not for this counter
0x0 = Triggers are not used
0x1 = Triggers are used as selected by the ETSEL field
0h = Triggers are not used.
1h = Triggers are used as selected by the IE, ITSEL and ETSEL fields.
8-5RESERVEDR/W0h
4-0ETSELR/W0hExternal Trigger Select.
This selects which System Event is used if the input filter selects trigger.
Triggers 0-15 are used to connect triggers generated by other timer modules. Refer to the SoC data sheet for details related to timer trigger sources.
Triggers 16 and 17 are connected to event manager subscriber ports.
Event lines 18-31 are reserved for future use.
0h = TRIGx = External trigger input from TIM x.
1h = TRIGx = External trigger input from TIM x.
2h = TRIGx = External trigger input from TIM x.
3h = TRIGx = External trigger input from TIM x.
4h = TRIGx = External trigger input from TIM x.
5h = TRIGx = External trigger input from TIM x.
6h = TRIGx = External trigger input from TIM x.
7h = TRIGx = External trigger input from TIM x.
8h = TRIGx = External trigger input from TIM x.
9h = TRIGx = External trigger input from TIM x.
Ah = TRIGx = External trigger input from TIM x.
Bh = TRIGx = External trigger input from TIM x.
Ch = TRIGx = External trigger input from TIM x.
Dh = TRIGx = External trigger input from TIM x.
Eh = TRIGx = External trigger input from TIM x.
Fh = TRIGx = External trigger input from TIM x.
10h = TRIG_SUBx = External trigger input from subscriber port x.
11h = TRIG_SUBx = External trigger input from subscriber port x.

25.3.58 RC (Offset = 18B4h) [Reset = 00000000h]

RC is shown in Figure 25-98 and described in Table 25-85.

Return to the Summary Table.

Repeat counter is to reduce interrupt overhead. The repeat counter provides the mechanism to suppress un-necessary interrupts;
reducing the number of interrupts generated by each event type to 1 for the program number of
periods. Specifically, the repeat timer may suppress Load, Compare (up/down, normal/shadow),
and Zero events.

Figure 25-98 RC
313029282726252423222120191817161514131211109876543210
RESERVEDRC
R-0hR-0h
Table 25-85 RC Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0RCR0hRepeat Counter Value
0h = Minimum value

FFh = Maximum Value

25.3.59 RCLD (Offset = 18B8h) [Reset = 00000000h]

RCLD is shown in Figure 25-99 and described in Table 25-86.

Return to the Summary Table.

The load register value is transferred to the counter when the counter load input is asserted.

Figure 25-99 RCLD
313029282726252423222120191817161514131211109876543210
RESERVEDRCLD
R/W-0hR/W-0h
Table 25-86 RCLD Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0RCLDR/W0hRepeat Counter Load Value
This field provides the value loaded into the
repeat counter at a load event following the
repeat counter value equaling 0.
0h = Minimum value

FFh = Maximum Value

25.3.60 QDIR (Offset = 18BCh) [Reset = 00000000h]

QDIR is shown in Figure 25-100 and described in Table 25-87.

Return to the Summary Table.

The QDIR register provides the direction of count which is intended for use when operating the counter in QEI.

Figure 25-100 QDIR
31302928272625242322212019181716
RESERVED
R-
1514131211109876543210
RESERVEDDIR
R-R-0h
Table 25-87 QDIR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0DIRR0hDirection of count
0h = Down (Phase B leads Phase A)
1h = Up (Phase A leads Phase B)

25.3.61 FCTL (Offset = 18D0h) [Reset = 00000000h]

FCTL is shown in Figure 25-101 and described in Table 25-88.

Return to the Summary Table.

The FCTL register controls the fault inputs, fault detection and error handling behavior.

Figure 25-101 FCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVEDFSENEXT2FSENEXT1FSENEXT0FSENAC2FSENAC1FSENAC0
R/W-R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TFIMRESERVEDFLFIRESERVEDFIEN
R/W-0hR/W-R/W-0hR/W-0hR/W-R/W-0h
Table 25-88 FCTL Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR/W0h
13FSENEXT2R/W0hSpecifies whether the external fault pin2 high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
12FSENEXT1R/W0hSpecifies whether the external fault pin1 high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
11FSENEXT0R/W0hSpecifies whether the external fault pin0 high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
10FSENAC2R/W0hSpecifies whether the COMP2 output high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
9FSENAC1R/W0hSpecifies whether the COMP1 output high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
8FSENAC0R/W0hSpecifies whether the COMP0 output high/low is treated as fault condition.
0h = Fault Input is active low.

1h = Fault Input is active high.
7TFIMR/W0hTrigger Fault Input Mask
Specifies whether the selected trigger participates as a fault input. If enabled and the trigger asserts, the trigger is treated as a fault.

0h = Selected trigger does not participate in fault condition generation
1h = Selected trigger participates in fault condition generation
6-5RESERVEDR/W0h
4-3FLR/W0hFault Latch mode
Specifies whether the fault condition is latched and configures the latch clear conditions.
0h = Overall fault condition is not dependent on the F bit in RIS
1h = Overall fault condition is dependent on the F bit in RIS
2h = Fault condition is latched. Fault condition is cleared on a zero event if the fault input is 0.
3h = Fault condition is latched. Fault condition is cleared on a load event if the fault input is 0.
2FIR/W0hFault Input
Specifies whether the overall fault condition is dependent on the sensed fault pin.

0h = Overall Fault condition is not dependent on sensed input.
1h = Overall Fault condition is dependent on sensed input.
1RESERVEDR/W0h
0FIENR/W0hFault Input Enable
This bit enables the input for fault detection.

0h = Fault Input Disabled

1h = Fault Input Enabled

25.3.62 FIFCTL (Offset = 18D4h) [Reset = 00000000h]

FIFCTL is shown in Figure 25-102 and described in Table 25-89.

Return to the Summary Table.

The FIFCTL register controls the filtering for the fault input.

Figure 25-102 FIFCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDFILTENCPVRESERVEDFP
R/W-R/W-0hR/W-0hR/W-R/W-0h
Table 25-89 FIFCTL Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4FILTENR/W0hFilter Enable
This bit controls whether the input is filtered by the input filter or bypasses to go directly to the optional pre-scale filter and then to the edge detect.

0h = Bypass

1h = Filtered.
3CPVR/W0hConsecutive Period/Voting Select
This bit controls whether the input filter uses a stricter consecutive period count or majority voting.

0h = Consecutive Periods.
The input must be at a specific logic level for the period defined by FP before it is passed to the filter output.

1h = Voting.
The filter ignores one clock of opposite logic over the filter period.
I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output
2RESERVEDR/W0h
1-0FPR/W0hFilter Period
This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.

0h = Filter Period 3
1h = Filter Period 5
2h = Filter Period 8