SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 24-6 lists the memory-mapped registers for the TRNG registers. All register offset addresses not listed in Table 24-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
10FCh | DESC | Module descriptions | Go | |
1100h | CTL | Controls the command and decimation rate | Go | |
1104h | STAT | Status register that informs health test results and last issued command | Go | |
1108h | DATA_CAPTURE | Captured word buffer of RNG data | Go | |
110Ch | TEST_RESULTS | Test results from TEST_ANA and TEST_DIG | Go | |
1110h | CLKDIVIDE | Clock Divider | Go |
Complex bit access types are encoded to fit into small table cells. Table 24-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 24-3 and described in Table 24-8.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 24-4 and described in Table 24-9.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 24-5 and described in Table 24-10.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
IIDX is shown in Figure 24-6 and described in Table 24-11.
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This register provides the highest priority enabled interrupt index. 0h means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, … 231 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0h.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No bit is set means there is no pending interrupt request 1h = Indicates that a health test has failed. The TRNG is in an error state until the interrupt is cleared. 2h = Indicates that the just issued command was rejected and is not being performed. 3h = Indicates that the current command/mode is done. This may have different meanings based on the mode: OFF --> Power has been turned off PWRUP_DIG --> Digital powerup tests are done PWRUP_ANA --> Analog powerup tests are done NORM_FUNC --> No IRQ, since mode runs indefinitely until a new command is issued 4h = Indicates that the captured word buffer is ready to be copied to memory |
IMASK is shown in Figure 24-7 and described in Table 24-12.
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Interrupt Mask. If a bit is set, then corresponding interrupt mask is set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IRQ_CAPTURED_RDY | IRQ_CMD_DONE | IRQ_CMD_FAIL | IRQ_HEALTH_FAIL | |||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | IRQ_CAPTURED_RDY | R/W | 0h | Mask for IRQ_CAPTURED_RDY. Indicates to the CPU that the Captured Word is ready to be read.
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
2 | IRQ_CMD_DONE | R/W | 0h | Mask for IRQ_CMD_DONE. Indicates that a command has finished
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
1 | IRQ_CMD_FAIL | R/W | 0h | Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | IRQ_HEALTH_FAIL | R/W | 0h | Mask for IRQ_HEALTH_FAIL. Indicates that a health test has failed.
0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
RIS is shown in Figure 24-8 and described in Table 24-13.
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Raw interrupt status reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IRQ_CAPTURED_RDY | IRQ_CMD_DONE | IRQ_CMD_FAIL | IRQ_HEALTH_FAIL | |||
R-X | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | IRQ_CAPTURED_RDY | R | 0h | Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not occur 1h = IRQ_CAPTURED_READY occurred |
2 | IRQ_CMD_DONE | R | 0h | Raw interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed.
0h = IRQ_CMD_DONE did not occur 1h = IRQ_CMD_DONE occurred |
1 | IRQ_CMD_FAIL | R | 0h | Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = IRQ_CMD_FAIL did not occur 1h = IRQ_CMD_FAIL occurred |
0 | IRQ_HEALTH_FAIL | R | 0h | Indicates to the CPU that any of the health tests have failed. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not occur 1h = IRQ_CAPTURED_READY occurred |
MIS is shown in Figure 24-9 and described in Table 24-14.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IRQ_CAPTURED_RDY | IRQ_CMD_DONE | IRQ_CMD_FAIL | IRQ_HEALTH_FAIL | |||
R-X | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | IRQ_CAPTURED_RDY | R | 0h | Masked interrupt result for CAPTURED_READY. Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine 1h = IRQ_CAPTURED_READY requests an interrupt service routine |
2 | IRQ_CMD_DONE | R | 0h | Masked interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine 1h = IRQ_CMD_DONE requests an interrupt service routine |
1 | IRQ_CMD_FAIL | R | 0h | Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = IRQ_CMD_FAIL did not request an interrupt service routine 1h = IRQ_CMD_FAIL requests an interrupt service routine |
0 | IRQ_HEALTH_FAIL | R | 0h | Masked interrupt result for HEALTH_FAIL. Indicates to the CPU that any of the health tests have failed for the latest 1024-bit window.
0h = IRQ_CAPTURED_READY did not request an interrupt service routine 1h = IRQ_CAPTURED_READY requests an interrupt service routine |
ISET is shown in Figure 24-10 and described in Table 24-15.
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ISET allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IRQ_CAPTURED_RDY | IRQ_CMD_DONE | IRQ_CMD_FAIL | IRQ_HEALTH_FAIL | |||
W- | W- | W- | W- | W- | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | IRQ_CAPTURED_RDY | W | 0h | Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect 1h = RIS bit corresponding to CAPTURED_READY is set |
2 | IRQ_CMD_DONE | W | 0h | Write to turn on CMD_DONE IRQ. Indicates that the last issued TRNG command has finished.
0h = Writing a 0 has no effect. 1h = RIS bit corresponding to CMD_DONE is set |
1 | IRQ_CMD_FAIL | W | 0h | Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Writing a 0 has no effect. 1h = RIS bit corresponding to CMD_FAIL is set |
0 | IRQ_HEALTH_FAIL | W | 0h | Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect 1h = RIS bit corresponding to HEALTH_FAIL is set |
ICLR is shown in Figure 24-11 and described in Table 24-16.
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Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IRQ_CAPTURED_RDY | IRQ_CMD_DONE | IRQ_CMD_FAIL | IRQ_HEALTH_FAIL | |||
W- | W- | W- | W- | W- | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | IRQ_CAPTURED_RDY | W | 0h | Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect 1h = RIS bit corresponding to CAPTURED_READY is cleared |
2 | IRQ_CMD_DONE | W | 0h | Write to turn off CMD_DONE IRQ. Indicates that the last issued TRNG command has finished.
0h = Writing a 0 has no effect. 1h = RIS bit corresponding to CMD_DONE is cleared |
1 | IRQ_CMD_FAIL | W | 0h | Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected.
0h = Writing a 0 has no effect. 1h = RIS bit corresponding to CMD_FAIL is cleared |
0 | IRQ_HEALTH_FAIL | W | 0h | Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt.
0h = Writing a 0 has no effect 1h = RIS bit corresponding to CAPTURED_READY is cleared |
DESC is shown in Figure 24-12 and described in Table 24-17.
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This register is used to specify clock source selection for any special modules that need to choose between MCLK and another special clock source. The register is not expected to be present on most standard SVT peripherals but may be present on modules such as the ADC. The register is not present on VDDCOREULP domain peripherals and will be reserved, reading 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-511h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | INSTNUM | MAJREV | MINREV | ||||||||||||
R-0h | R-0h | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 511h | Module Identifier - An internal TI page has been created to request unique module IDs |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance* |
11-8 | INSTNUM | R | 0h | Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances |
7-4 | MAJREV | R | 0h | Major rev of the IP |
3-0 | MINREV | R | 0h | Minor rev of the IP |
CTL is shown in Figure 24-13 and described in Table 24-18.
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Affects various parameters of the TRNG system
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PWRUP_PSTART_CFG | PWRUP_PCHRG_CFG | PWRUP_CLKDIV | ||||
R/W-X | R/W-2h | R/W-2h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DECIM_RATE | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMD | ||||||
R/W-X | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R/W | X | |
20-19 | PWRUP_PSTART_CFG | R/W | 2h | Configure pusle startup sequence length b00 = Disabled b01 = rise at 10us, fall at 50us b10 = rise at 10us, fall at 70us (default) b11 = rise at 10us, fall at 90us |
18-17 | PWRUP_PCHRG_CFG | R/W | 2h | Configure PCHARGE sequence length b00 = Disabled b01 = 20 us PCHARGE b10 = 30 us PCHARGE (default) b11 = 40 us PCHARGE |
16 | PWRUP_CLKDIV | R/W | 0h | When '1', the powerup sequence will take twice as long (i.e., clock frequency halved) |
15-11 | RESERVED | R/W | X | |
10-8 | DECIM_RATE | R/W | 0h | Set decimation rate. Decimate by n 0x0 = Decimation by 1 (no decimation) 0x1 = Decimation by 2 (Skip every other sample) … 0x7 = Decimation by 8 (Take every 8th sample) |
7-2 | RESERVED | R/W | X | |
1-0 | CMD | R/W | 0h | Sets the TRNG mode through a command. The mode will not be updated until the previous command is done, as indicated by IRQ_CMD_DONE. 00 --> OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA 11 --> NORM_FUNC 0h = Turns the power off of the analog source and clocks the digital interface 1h = Initiates the powerup test sequence for the digital components. This verifies that the digital components are properly working. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bits 0:6 in TEST_RESULTS register 2h = Initiates the powerup test sequence for the analog TRNG. This verifies that the analog component is generating sequences with enough entropy. IRQ_CMD_DONE indicates that the test is done. The results of this test are in bit 7 in TEST_RESULTS register 3h = Normal operating mode for TRNG. All components are turned on. |
STAT is shown in Figure 24-14 and described in Table 24-19.
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Status register that informs health test result, last issued command, and current FSM state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FSM_STATE | ||||||
R-X | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ISSUED_CMD | ||||||
R-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REP_FAIL | ADAP_FAIL | |||||
R-X | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-16 | FSM_STATE | R | 0h | Current state of the front end FSM (behind a clock domain crossing). 2 reads are REQUIRED as there is a chance of metastability when reading this States: 0000: OFF 0001: PWRUP_ES 0011: NORM_FUNC 0111: TEST_DIG 1011: TEST_ANA 1010: ERROR 0010: PWRDOWN_ES |
15-10 | RESERVED | R | X | |
9-8 | ISSUED_CMD | R | 0h | Indicates the last accepted command that is issued to the TRNG interface. Upon writing a valid command, this register will update and the command will be in progress until CMD_DONE_IRQ is set. CMD_DONE_IRQ indicates that the state is in PWROFF, NORM_FUNC, or ERROR. These states will accept new commands. 00 --> OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA 11 --> NORM_FUNC |
7-2 | RESERVED | R | X | |
1 | REP_FAIL | R | 0h | Indicates that the repetition counter test caused the most recent failure. Thus, the health count numbers are most likely not for a complete 1024-bit window. |
0 | ADAP_FAIL | R | 0h | Indicates that the Adaptive Proportion Test (1,2,3, or 4-bit counters) failed by having too many or too few counted samples in the last 1024 bit window. |
DATA_CAPTURE is shown in Figure 24-15 and described in Table 24-20.
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Captured data from decimation block
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUFFER | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BUFFER | R | 0h | Captured Data from the Decimation Block |
TEST_RESULTS is shown in Figure 24-16 and described in Table 24-21.
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Includes a bit describing which startup test failed. The first 8 bits check the condition of the digital components in the digital startup validation check and the 9th bit checks that the entropy source is producing samples that have enough entropy. This register will read all '0s when a command is not finished. Each of the tests are active low, indicating a failed test with '0' and a passed test with '1'.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ANA_TEST | ||||||
R-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIG_TEST | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | X | |
8 | ANA_TEST | R | 0h | Runs through 4096 samples from an enabled entropy source and verifies that none of the health tests failed, indicating sufficient entropy was produced by the analog components |
7-0 | DIG_TEST | R | 0h | Bit 0 indicates if the first decimation rate test and health test(verifies conditioning, decimation, and captured buffer) fails and Bit 1 indicates if the second decimation test and health test fails Bit 0 - decim_test0 (decim = 0x0) Bit 1 - decim_test1 (decim = 0x1) ... |
CLKDIVIDE is shown in Figure 24-17 and described in Table 24-22.
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This register is used to specify module-specific divide ratio of the functional clock,and it only supports even division for TRNG.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock
0h = Do not divide clock source 1h = Divide clock source by 2 3h = Divide clock source by 4 5h = Divide clock source by 6 7h = Divide clock source by 8 |