SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 17-7 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 17-7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
4h | SCLK | SCLK | Go | |
8h | MOSI | MOSI | Go | |
Ch | MISO | MISO | Go | |
18h | CS0 | SPI Chip Select 0 | Go | |
1Ch | CS1_MISO1 | SPI Chip Select 1 | Go | |
20h | CS2_MISO2 | SPI Chip Select 2 | Go | |
24h | CS3_CD_MISO3 | SPI Chip Select 3 | Go | |
204h | SCLK | FUPDATE version of SCLK | Go | |
208h | MOSI | FUPDATE version of MOSI | Go | |
20Ch | MISO | FUPDATE version of MISO | Go | |
218h | CS0 | FUPDATE version of CS0 | Go | |
21Ch | CS1_MISO1 | FUPDATE version of CS1 | Go | |
220h | CS2_MISO2 | FUPDATE version of CS2 | Go | |
224h | CS3_CD_MISO3 | FUPDATE version of CS3 | Go | |
480h | CPU_CONNECT_0 | CPU Connect | Go | |
504h | DMA_MAP_RX | DMA Map | Go | |
505h | DMA_TRIG_RX | DMA Trigger | Go | |
506h | DMA_ENTRY_RX | DMA Entry | Go | |
508h | DMA_MAP_TX | DMA Map | Go | |
509h | DMA_TRIG_TX | DMA Trigger | Go | |
50Ah | DMA_ENTRY_TX | DMA Entry | Go | |
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
808h | CLKCFG | Peripheral Clock Configuration Register | Go | |
814h | STAT | Status Register | Go | |
1000h | CLKDIV | Clock Divider | Go | |
1004h | CLKSEL | Clock Select for Ultra Low Power peripherals | Go | |
1018h | PDBGCTL | Peripheral Debug Control | Go | |
1020h | IIDX | Interrupt Index Register | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt Index Register | DMA_TRIG_RX | Go |
1058h | IMASK | Interrupt mask | DMA_TRIG_RX | Go |
1060h | RIS | Raw interrupt status | DMA_TRIG_RX | Go |
1068h | MIS | Masked interrupt status | DMA_TRIG_RX | Go |
1070h | ISET | Interrupt set | DMA_TRIG_RX | Go |
1078h | ICLR | Interrupt clear | DMA_TRIG_RX | Go |
1080h | IIDX | Interrupt Index Register | DMA_TRIG_TX | Go |
1088h | IMASK | Interrupt mask | DMA_TRIG_TX | Go |
1090h | RIS | Raw interrupt status | DMA_TRIG_TX | Go |
1098h | MIS | Masked interrupt status | DMA_TRIG_TX | Go |
10A0h | ISET | Interrupt set | DMA_TRIG_TX | Go |
10A8h | ICLR | Interrupt clear | DMA_TRIG_TX | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10E4h | INTCTL | Interrupt control register | Go | |
1100h | CTL0 | SPI control register 0 | Go | |
1104h | CTL1 | SPI control register 1 | Go | |
1108h | CLKCTL | Clock prescaler and divider register. | Go | |
110Ch | IFLS | Interrupt FIFO Level Select Register | Go | |
1110h | STAT | Status Register | Go | |
1130h | RXDATA | RXDATA Register | Go | |
1140h | TXDATA | TXDATA Register | Go | |
1E00h | TEST0 | Test 0 Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 17-8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 |
Read Returns 0s |
Write Type | ||
W | W | Write |
WK | W K |
Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
SCLK is shown in Figure 17-9 and described in Table 17-9.
Return to the Summary Table.
SCLK Signal Controller : Clock Output Peripheral: Clock Input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
MOSI is shown in Figure 17-10 and described in Table 17-10.
Return to the Summary Table.
MOSI Signal Controller : Data Output Peripheral: Data Input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
MISO is shown in Figure 17-11 and described in Table 17-11.
Return to the Summary Table.
MISO Signal Controller : Data Input Peripheral: Data Output
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
CS0 is shown in Figure 17-12 and described in Table 17-12.
Return to the Summary Table.
SPI Chip Select 0: Controller : Output Peripheral: Input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
CS1_MISO1 is shown in Figure 17-13 and described in Table 17-13.
Return to the Summary Table.
SPI Chip Select 1 / MISO1 Controller : Output / Input Peripheral: - / Output
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
CS2_MISO2 is shown in Figure 17-14 and described in Table 17-14.
Return to the Summary Table.
SPI Chip Select 2 / MISO2 Controller : Output / Input Peripheral: - / Output
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
CS3_CD_MISO3 is shown in Figure 17-15 and described in Table 17-15.
Return to the Summary Table.
SPI Chip Select 3 / Command Data / MISO3 Controller : Output / Output / Input Peripheral: - / - / Output
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | GFLT | SLEW | WCOMP | WUEN | INV | HIGHZ1 | HIGHZ0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSTATE | RESERVED | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 0h | |
30 | GFLT | R/W | 0h | Glitch Filter Enable 0h = No internal glitch filter 1h = Use internal glitch filter |
29 | SLEW | R/W | 0h | Reserved Slew Rate Control 0h = No Slew Rate Control 1h = Use Slew Rate Control |
28 | WCOMP | R/W | 0h | Wake up compare value 0h = Match 0 will wake 1h = Match 1 will wake |
27 | WUEN | R/W | 0h | Wake up enable 0h = Wake up not enabled 1h = Wake up enabled |
26 | INV | R/W | 0h | Invert digital input/output relative to peripheral/GPIO 0h = Input and output are non-inverted 1h = Input and output are inverted |
25 | HIGHZ1 | R/W | 0h | High-Z instead of high output 0h = Pin can be driven high 1h = Pin is tri-stated instead of driven high |
24 | HIGHZ0 | R/W | 0h | High-Z instead of low output 0h = Pin can be driven low 1h = Pin is tri-stated instead of driven low |
23 | RESERVED | R/W | 0h | |
22-20 | DRV | R/W | 0h | Drive strength options 0h = Lowest drive strength 1h = Drive strength 2/8 2h = Drive strength 3/8 3h = Drive strength 4/8 4h = Drive strength 5/8 5h = Drive strength 6/8 6h = Drive strength 7/8 7h = Highest drive strength |
19 | HYSTEN | R/W | 0h | Hysteresis enable 0h = No hysteresis 1h = Hysteresis on |
18 | INENA | R/W | 0h | Input enable 0h = Inputs 0 to connected core 1h = Inputs IO pad value to connected core |
17 | PIPU | R/W | 0h | Pull up enable 0h = No pull up 1h = Pull up |
16 | PIPD | R/W | 0h | Pull down enable 0h = No pull down 1h = Pull down |
15-14 | GSTATE | R/W | 0h | GPIO Channel State 0h = G-Channel is in Unassigned State 1h = G-Channel is in Handover State 2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
13-8 | RESERVED | R/W | 0h | |
7-6 | PSTATE | R/W | 0h | Peripheral-Analog Channel State 0h = P-Channel is in Unassigned State 1h = P-Channel is in Handover State 2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state) 3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned) |
5-0 | RESERVED | R/W | 0h |
SCLK is shown in Figure 17-16 and described in Table 17-16.
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FUPDATE version of SCLK
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
MOSI is shown in Figure 17-17 and described in Table 17-17.
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FUPDATE version of MOSI
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
MISO is shown in Figure 17-18 and described in Table 17-18.
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FUPDATE version of MISO
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
CS0 is shown in Figure 17-19 and described in Table 17-19.
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FUPDATE version of CS0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
CS1_MISO1 is shown in Figure 17-20 and described in Table 17-20.
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FUPDATE version of CS1_MISO1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
CS2_MISO2 is shown in Figure 17-21 and described in Table 17-21.
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FUPDATE version of CS2_MISO2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
CS3_CD_MISO3 is shown in Figure 17-22 and described in Table 17-22.
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FUPDATE version of CS3_CD_MISO3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | IOADDR | ||||||
W-0h | W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IOADDR | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IOADDR | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOADDR | LOCK | GSEL | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | W | 0h | |
27-2 | IOADDR | W | 0h | IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion. |
1 | LOCK | W | 0h | Sets lock bit 0h = Writing this value has no effect 1h = Set channel lock bit |
0 | GSEL | W | 0h | GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update 0h = Select the P-Channel for the F update 1h = Select the G-Channel for the F update |
CPU_CONNECT_0 is shown in Figure 17-23 and described in Table 17-23.
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Directly connect peripheral publisher port to application processor
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUSS0_CONN | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | CPUSS0_CONN | R/W | 0h | CPUSS0 connect bit. 0h = The CPU is not connected. 1h = The CPU is connected. |
0 | RESERVED | R/W | 0h |
DMA_MAP_RX is shown in Figure 17-24 and described in Table 17-24.
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Trigger port ID in the DMA for this peripheral trigger
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIG_ID | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | |
6-0 | TRIG_ID | R | 0h | The trigger port ID in the DMA for this peripheral trigger 0h = No trigger selected 1h = Trigger 1 selected 7Fh = Trigger 127 selected |
DMA_TRIG_RX is shown in Figure 17-25 and described in Table 17-25.
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Trigger control and status register for this peripheral trigger
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRHLD | TRIGLOST | STATECLR | STATE | |||
R/W-0h | R-0h | R-0h | R-0/W-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-4 | THRHLD | R | 0h | The threshold for the DMA to accept the trigger request. 0h = Lowest threshold possible 6h = Highest threshold possible |
3 | TRIGLOST | R | 0h | Sticky flag that is set whenever a trigger request is received while the trigger port is in TRIGGER_PEND or TRIGGERED. Cleared by writing to STATECLR. 0h = Trigger not lost 1h = Trigger was lost |
2 | STATECLR | R-0/W | 0h | Clear trigger state. Writing 1 to this register clears any pending DMA trigger on this port and transitions the port to Untriggered state. 0h = Writing 0 has no effect 1h = Clear DMA trigger |
1-0 | STATE | R | 0h | Returns the current state of the DMA tx trigger port 0h = Channel was not triggered 1h = Channel trigger is pending 2h = Channel was triggered |
DMA_ENTRY_RX is shown in Figure 17-26 and described in Table 17-26.
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Descriptor connect to peripheral DMA trigger
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ENTRY_ID | ||||||
R/W- | R/W-FFFh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENTRY_ID | |||||||
R/W-FFFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | |
11-0 | ENTRY_ID | R/W | FFFh | The ID of the DMA descriptor that this trigger is routed to. This allows to ensure that another DMA channel could not listen or influence the DMA channel responsible for handling the data of this peripheral.
0h = DCLB index i=0-15. This can only be used with dedicated DCLBs. Fh = DCLB index i=0-15. This can only be used with dedicated DCLBs. 10h = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system. FFEh = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system. FFFh = Trigger not enabled |
DMA_MAP_TX is shown in Figure 17-27 and described in Table 17-27.
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Trigger port ID in the DMA for this peripheral trigger
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIG_ID | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | |
6-0 | TRIG_ID | R | 0h | The trigger port ID in the DMA for this peripheral trigger 0h = No trigger selected 1h = Trigger 1 selected 7Fh = Trigger 127 selected |
DMA_TRIG_TX is shown in Figure 17-28 and described in Table 17-28.
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Trigger control and status register for this peripheral trigger
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRHLD | TRIGLOST | STATECLR | STATE | |||
R/W-0h | R-0h | R-0h | R-0/W-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-4 | THRHLD | R | 0h | The threshold for the DMA to accept the trigger request. 0h = Lowest threshold possible 6h = Highest threshold possible |
3 | TRIGLOST | R | 0h | Sticky flag that is set whenever a trigger request is received while the trigger port is in TRIGGER_PEND or TRIGGERED. Cleared by writing to STATECLR. 0h = Trigger not lost 1h = Trigger was lost |
2 | STATECLR | R-0/W | 0h | Clear trigger state. Writing 1 to this register clears any pending DMA trigger on this port and transitions the port to Untriggered state. 0h = Writing 0 has no effect 1h = Clear DMA trigger |
1-0 | STATE | R | 0h | Returns the current state of the DMA tx trigger port 0h = Channel was not triggered 1h = Channel trigger is pending 2h = Channel was triggered |
DMA_ENTRY_TX is shown in Figure 17-29 and described in Table 17-29.
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Descriptor connect to peripheral DMA trigger
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ENTRY_ID | ||||||
R/W- | R/W-FFFh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENTRY_ID | |||||||
R/W-FFFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R/W | 0h | |
11-0 | ENTRY_ID | R/W | FFFh | The ID of the DMA descriptor that this trigger is routed to. This allows to ensure that another DMA channel could not listen or influence the DMA channel responsible for handling the data of this peripheral.
0h = DCLB index i=0-15. This can only be used with dedicated DCLBs. Fh = DCLB index i=0-15. This can only be used with dedicated DCLBs. 10h = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system. FFEh = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system. FFFh = Trigger not enabled |
PWREN is shown in Figure 17-30 and described in Table 17-30.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change 26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power
KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 17-31 and described in Table 17-31.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
CLKCFG is shown in Figure 17-32 and described in Table 17-32.
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Peripheral Clock Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BLOCKASYNC | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to Allow State Change -- 0xA9 A9h = key value to allow change field of GPRCM |
23-9 | RESERVED | R/W | 0h | |
8 | BLOCKASYNC | R/W | 0h | Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0h = Not block async clock request 1h = Block async clock request |
7-0 | RESERVED | R/W | 0h |
STAT is shown in Figure 17-33 and described in Table 17-33.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKDIV is shown in Figure 17-34 and described in Table 17-34.
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This register is used to specify module-specific divide ratio of the functional clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |
CLKSEL is shown in Figure 17-35 and described in Table 17-35.
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Clock source selection for peripherals
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYSCLK_SEL | MFCLK_SEL | LFCLK_SEL | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | SYSCLK_SEL | R/W | 0h | Selects SYSCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
2 | MFCLK_SEL | R/W | 0h | Selects MFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
1 | LFCLK_SEL | R/W | 0h | Selects LFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
0 | RESERVED | R/W | 0h |
PDBGCTL is shown in Figure 17-36 and described in Table 17-36.
Return to the Summary Table.
This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W- | R/W-1h | R/W-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | SOFT | R/W | 1h | Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption |
0 | FREE | R/W | 1h | Free run control 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input |
IIDX is shown in Figure 17-37 and described in Table 17-37.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status 00h = No interrupt pending 1h = RX FIFO Overflow Event/interrupt pending 2h = Transmit Parity Event/interrupt pending 3h = SPI receive time-out interrupt 4h = Receive Event/interrupt pending 5h = Transmit Event/interrupt pending 6h = Transmit Buffer Empty Event/interrupt pending 7h = End of Transmit Event/interrupt pending 8h = DMA Done for Receive Event/interrupt pending 9h = DMA Done for Transmit Event/interrupt pending Ah = TX FIFO underflow interrupt Bh = RX FIFO Full Interrupt |
IMASK is shown in Figure 17-38 and described in Table 17-38.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFULL | TXFIFO_UNF | DMA_DONE_TX | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_DONE_RX | IDLE | TXEMPTY | TX | RX | RTOUT | PER | RXFIFO_OVF |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R/W | 0h | |
10 | RXFULL | R/W | 0h | RX FIFO Full Interrupt Mask 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | TXFIFO_UNF | R/W | 0h | TX FIFO underflow interrupt mask 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | DMA_DONE_TX | R/W | 0h | DMA Done 1 event for TX event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | DMA_DONE_RX | R/W | 0h | DMA Done 1 event for RX event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | IDLE | R/W | 0h | SPI Idle event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | TXEMPTY | R/W | 0h | Transmit FIFO Empty event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | TX | R/W | 0h | Transmit FIFO event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3 | RX | R/W | 0h | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | RTOUT | R/W | 0h | Enable SPI Receive Time-Out event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | PER | R/W | 0h | Parity error event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | RXFIFO_OVF | R/W | 0h | RXFIFO overflow event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 17-39 and described in Table 17-39.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFULL | TXFIFO_UNF | DMA_DONE_TX | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_DONE_RX | IDLE | TXEMPTY | TX | RX | RTOUT | PER | RXFIFO_OVF |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | |
10 | RXFULL | R | 0h | RX FIFO Full Interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
9 | TXFIFO_UNF | R | 0h | TX FIFO Underflow Interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
8 | DMA_DONE_TX | R | 0h | DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMA_DONE_RX | R | 0h | DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral. 0h = Interrupt did not occur 1h = Interrupt occurred |
6 | IDLE | R | 0h | SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low. 0h = Interrupt did not occur 1h = Interrupt occurred |
5 | TXEMPTY | R | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register. 0h = Interrupt did not occur 1h = Interrupt occurred |
4 | TX | R | 0h | Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0h = Interrupt did not occur 1h = Interrupt occurred |
3 | RX | R | 0h | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | SPI Receive Time-Out event. 0h = Interrupt did not occur 1h = Interrupt occurred |
1 | PER | R | 0h | Parity error event: this bit is set if a Parity error has been detected 0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RXFIFO_OVF | R | 0h | RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Figure 17-40 and described in Table 17-40.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFULL | TXFIFO_UNF | DMA_DONE_TX | ||||
R-0h | R-0h | R-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_DONE_RX | IDLE | TXEMPTY | TX | RX | RTOUT | PER | RXFIFO_OVF |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | |
10 | RXFULL | R | 0h | RX FIFO Full Interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
9 | TXFIFO_UNF | R | 0h | TX FIFO underflow interrupt 0h = Interrupt did not occur 1h = Interrupt occurred |
8 | DMA_DONE_TX | R | 0h | Masked DMA Done 1 event for TX. 0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMA_DONE_RX | R | 0h | Masked DMA Done 1 event for RX. 0h = Interrupt did not occur 1h = Interrupt occurred |
6 | IDLE | R | 0h | Masked SPI IDLE mode event. 0h = Interrupt did not occur 1h = Interrupt occurred |
5 | TXEMPTY | R | 0h | Masked Transmit FIFO Empty event. 0h = Interrupt did not occur 1h = Interrupt occurred |
4 | TX | R | 0h | Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached. 0h = Interrupt did not occur 1h = Interrupt occurred |
3 | RX | R | 0h | Masked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | Masked SPI Receive Time-Out Interrupt. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | PER | R | 0h | Masked Parity error event: this bit if a Parity error has been detected 0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RXFIFO_OVF | R | 0h | Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected. 0h = Interrupt did not occur 1h = Interrupt occurred |
ISET is shown in Figure 17-41 and described in Table 17-41.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFULL | TXFIFO_UNF | DMA_DONE_TX | ||||
W-0h | W-0h | W-0h | W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_DONE_RX | IDLE | TXEMPTY | TX | RX | RTOUT | PER | RXFIFO_OVF |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | W | 0h | |
10 | RXFULL | W | 0h | Set RX FIFO Full Event 0h = Writing has no effect 1h = Set Interrupt |
9 | TXFIFO_UNF | W | 0h | Set TX FIFO Underflow Event 0h = Writing has no effect 1h = Set interrupt |
8 | DMA_DONE_TX | W | 0h | Set DMA Done 1 event for TX. 0h = Writing 0 has no effect 1h = Set Interrupt |
7 | DMA_DONE_RX | W | 0h | Set DMA Done 1 event for RX. 0h = Writing 0 has no effect 1h = Set Interrupt |
6 | IDLE | W | 0h | Set SPI IDLE mode event. 0h = Writing 0 has no effect 1h = Set Interrupt |
5 | TXEMPTY | W | 0h | Set Transmit FIFO Empty event. 0h = Writing 0 has no effect 1h = Set Interrupt |
4 | TX | W | 0h | Set Transmit FIFO event. 0h = Writing 0 has no effect 1h = Set Interrupt |
3 | RX | W | 0h | Set Receive FIFO event. 0h = Writing 0 has no effect 1h = Set Interrupt |
2 | RTOUT | W | 0h | Set SPI Receive Time-Out Event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
1 | PER | W | 0h | Set Parity error event. 0h = Writing 0 has no effect 1h = Set Interrupt |
0 | RXFIFO_OVF | W | 0h | Set RXFIFO overflow event. 0h = Writing 0 has no effect 1h = Set Interrupt |
ICLR is shown in Figure 17-42 and described in Table 17-42.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFULL | TXFIFO_UNF | DMA_DONE_TX | ||||
W-0h | W-0h | W-0h | W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_DONE_RX | IDLE | TXEMPTY | TX | RX | RTOUT | PER | RXFIFO_OVF |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | W | 0h | |
10 | RXFULL | W | 0h | Clear RX FIFO underflow event 0h = Writing has no effect 1h = Clear interrupt |
9 | TXFIFO_UNF | W | 0h | Clear TXFIFO underflow event 0h = Writing has no effect 1h = Clear interrupt |
8 | DMA_DONE_TX | W | 0h | Clear DMA Done 1 event for TX. 0h = Writing 0 has no effect 1h = Clear Interrupt |
7 | DMA_DONE_RX | W | 0h | Clear DMA Done 1 event for RX. 0h = Writing 0 has no effect 1h = Clear Interrupt |
6 | IDLE | W | 0h | Clear SPI IDLE mode event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
5 | TXEMPTY | W | 0h | Clear Transmit FIFO Empty event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
4 | TX | W | 0h | Clear Transmit FIFO event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
3 | RX | W | 0h | Clear Receive FIFO event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
2 | RTOUT | W | 0h | Clear SPI Receive Time-Out Event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
1 | PER | W | 0h | Clear Parity error event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
0 | RXFIFO_OVF | W | 0h | Clear RXFIFO overflow event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
IIDX is shown in Figure 17-43 and described in Table 17-43.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status 00h = No interrupt pending 3h = SPI receive time-out interrupt 4h = Receive Event/interrupt pending |
IMASK is shown in Figure 17-44 and described in Table 17-44.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX | RTOUT | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | RX | R/W | 0h | Receive FIFO event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | RTOUT | R/W | 0h | SPI Receive Time-Out event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1-0 | RESERVED | R/W | 0h |
RIS is shown in Figure 17-45 and described in Table 17-45.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX | RTOUT | RESERVED | ||||
R- | R-0h | R-0h | R- | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | RX | R | 0h | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | SPI Receive Time-Out Event. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1-0 | RESERVED | R | 0h |
MIS is shown in Figure 17-46 and described in Table 17-46.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX | RTOUT | RESERVED | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | RX | R | 0h | Receive FIFO event mask. 0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | SPI Receive Time-Out event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1-0 | RESERVED | R | 0h |
ISET is shown in Figure 17-47 and described in Table 17-47.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX | RTOUT | RESERVED | ||||
W-0h | W-0h | W-0h | W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | RX | W | 0h | Set Receive FIFO event. 0h = Writing 0 has no effect 1h = Set Interrupt |
2 | RTOUT | W | 0h | Set SPI Receive Time-Out event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
1-0 | RESERVED | W | 0h |
ICLR is shown in Figure 17-48 and described in Table 17-48.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX | RTOUT | RESERVED | ||||
W-0h | W-0h | W-0h | W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | W | 0h | |
3 | RX | W | 0h | Clear Receive FIFO event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
2 | RTOUT | W | 0h | Clear SPI Receive Time-Out event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
1-0 | RESERVED | W | 0h |
IIDX is shown in Figure 17-49 and described in Table 17-49.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status 00h = No interrupt pending 5h = Transmit Event/interrupt pending |
IMASK is shown in Figure 17-50 and described in Table 17-50.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX | RESERVED | |||||||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | 0h | |
4 | TX | R/W | 0h | Transmit FIFO event mask. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3-0 | RESERVED | R/W | 0h |
RIS is shown in Figure 17-51 and described in Table 17-51.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX | RESERVED | |||||||||||||
R- | R-0h | R- | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | |
4 | TX | R | 0h | Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A
write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. 0h = Interrupt did not occur 1h = Interrupt occurred |
3-0 | RESERVED | R | 0h |
MIS is shown in Figure 17-52 and described in Table 17-52.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX | RESERVED | |||||||||||||
R-0h | R-0h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | |
4 | TX | R | 0h | Masked Transmit FIFO event 0h = Interrupt did not occur 1h = Interrupt occurred |
3-0 | RESERVED | R | 0h |
ISET is shown in Figure 17-53 and described in Table 17-53.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX | RESERVED | |||||||||||||
W-0h | W-0h | W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | W | 0h | |
4 | TX | W | 0h | Set Transmit FIFO event. 0h = Writing 0 has no effect 1h = Set Interrupt |
3-0 | RESERVED | W | 0h |
ICLR is shown in Figure 17-54 and described in Table 17-54.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX | RESERVED | |||||||||||||
W-0h | W-0h | W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | W | 0h | |
4 | TX | W | 0h | Clear Transmit FIFO event. 0h = Writing 0 has no effect 1h = Clear Interrupt |
3-0 | RESERVED | W | 0h |
EVT_MODE is shown in Figure 17-55 and described in Table 17-55.
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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT2_CFG | INT1_CFG | INT0_CFG | ||||
R/W- | R-2h | R-2h | R-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5-4 | INT2_CFG | R | 2h | Event line mode select for event corresponding to none.INT_EVENT2 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
3-2 | INT1_CFG | R | 2h | Event line mode select for event corresponding to none.INT_EVENT1 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 1h | Event line mode select for event corresponding to none.INT_EVENT0 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
INTCTL is shown in Figure 17-56 and described in Table 17-56.
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Interrupt control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTEVAL | ||||||
R/W- | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | INTEVAL | W | 0h | Writing a 1 to this field re-evaluates the interrupt sources. 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. |
CTL0 is shown in Figure 17-57 and described in Table 17-57.
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SPI control register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CSCLR | CSSEL | RESERVED | SPH | SPO | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PACKEN | FRF | DSS | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | 0h | |
14 | CSCLR | R/W | 0h | Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.CP=0. 0h = Disable automatic clear of shift register when CS goes to disable. 1h = Enable automatic clear of shift register when CS goes to disable. |
13-12 | CSSEL | R/W | 0h | Select the CS line to control on data transfer This bit is applicable for both controller/target mode 0h (R/W) = CS line select: 0 1h (R/W) = CS line select: 1 2h (R/W) = CS line select: 2 3h (R/W) = CS line select: 3 |
11-10 | RESERVED | R/W | 0h | |
9 | SPH | R/W | 0h | CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0h = Data is captured on the first clock edge transition. 1h = Data is captured on the second clock edge transition. |
8 | SPO | R/W | 0h | CLKOUT polarity (Motorola SPI frame format only) 0h = SPI produces a steady state LOW value on the CLKOUT 1h = SPI produces a steady state HIGH value on the CLKOUT |
7 | PACKEN | R/W | 0h | Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP 0h = Packing feature disabled 1h = Packing feature enabled |
6-5 | FRF | R/W | 0h | Frame format Select 0h = Motorola SPI frame format (3 wire mode) 1h = Motorola SPI frame format (4 wire mode) 2h = TI synchronous serial frame format 3h = National Microwire frame format |
4-0 | DSS | R/W | 0h | Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit 3h (R/W) = Data Size Select bits: 4 4h (R/W) = Data Size Select bits: 5 5h (R/W) = Data Size Select bits: 6 6h (R/W) = Data Size Select bits: 7 7h (R/W) = Data Size Select bits: 8 8h (R/W) = Data Size Select bits: 9 9h (R/W) = Data Size Select bits: 10 Ah (R/W) = Data Size Select bits: 11 Bh (R/W) = Data Size Select bits: 12 Ch (R/W) = Data Size Select bits: 13 Dh (R/W) = Data Size Select bits: 14 Eh (R/W) = Data Size Select bits: 15 Fh (R/W) = Data Size Select bits: 16 |
CTL1 is shown in Figure 17-58 and described in Table 17-58.
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SPI control register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RXTIMEOUT | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
REPEATTX | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CDMODE | CDENABLE | RESERVED | PTEN | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PES | PREN | MSB | POD | CP | LBM | ENABLE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | |
29-24 | RXTIMEOUT | R/W | 0h | Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection
and divider in the Controller mode configuration. A value of 0 disables this function. 0h = Smallest value 3Fh = Highest possible value |
23-16 | REPEATTX | R/W | 0h | Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will
be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used
to clean a transfer or to pull a certain amount of data by a peripheral. 0h = Smallest value FFh = Highest possible value |
15-12 | CDMODE | R/W | 0h | Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low. 0h = Manual mode: Data 0h = Smallest value Fh = Manual mode: Command |
11 | CDENABLE | R/W | 0h | Command/Data Mode enable 0h = CS3 is used for Chip Select 1h = CS3 is used as CD signal |
10-9 | RESERVED | R/W | 0h | |
8 | PTEN | R/W | 0h | Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes. 0h = Parity transmission is disabled 1h = Parity transmission is enabled |
7 | RESERVED | R/W | 0h | |
6 | PES | R/W | 0h | Even Parity Select 0h = Odd Parity mode 1h = Even Parity mode |
5 | PREN | R/W | 0h | Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set. 0h = Disable Parity receive function 1h = Enable Parity receive function |
4 | MSB | R/W | 0h | MSB first select. Controls the direction of the receive and transmit shift register. 0h = LSB first 1h = MSB first |
3 | POD | R/W | 0h | Peripheral-mode: Data output disabled This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line. POD can be used by the SPI peripheral to disable driving data on the line. 0h = SPI can drive the MISO output in peripheral mode. 1h = SPI cannot drive the MISO output in peripheral mode. |
2 | CP | R/W | 1h | Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0h = Select Peripheral mode 1h = Select Controller Mode |
1 | LBM | R/W | 0h | Loop back mode 0h = Disable loopback mode 1h = Enable loopback mode |
0 | ENABLE | R/W | 0h | SPI enable 0h = Disable module function 1h = Enable module function |
CLKCTL is shown in Figure 17-59 and described in Table 17-59.
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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DSAMPLE | RESERVED | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SCR | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | DSAMPLE | R/W | 0h | Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the data sheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations. 0h = Smallest value Fh = Highest possible value |
27-10 | RESERVED | R/W | 0h | |
9-0 | SCR | R/W | 0h | Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI functional clock frequency)/((SCR+1)×2). SCR is a value from 0-1023. 0h = Smallest value 3FFh = Highest possible value |
IFLS is shown in Figure 17-60 and described in Table 17-60.
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The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXIFLSEL | TXIFLSEL | |||||||||||||
R/W-0h | R/W-2h | R/W-2h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5-3 | RXIFLSEL | R/W | 2h | SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 0h = Reserved 1h = RX FIFO >= 1/4 full 2h = RX FIFO >= 1/2 full (default) 3h = RX FIFO >= 3/4 full 4h = Reserved 5h = RX FIFO is full 6h = Reserved 7h = Trigger when RX FIFO contains >= 1 frame |
2-0 | TXIFLSEL | R/W | 2h | SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 0h = Reserved 1h = TX FIFO <= 3/4 empty 2h = TX FIFO <= 1/2 empty (default) 3h = TX FIFO <= 1/4 empty 4h = Reserved 5h = TX FIFO is empty 6h = Reserved 7h = Trigger when TX FIFO has >= 1 frame free. |
STAT is shown in Figure 17-61 and described in Table 17-61.
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Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSY | RNF | RFE | TNF | TFE | ||
R- | R-0h | R-1h | R-1h | R-1h | R-1h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | |
4 | BUSY | R | 0h | Busy 0h = SPI is in idle mode. 1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. |
3 | RNF | R | 1h | Receive FIFO not full 0h = Receive FIFO is full. 1h = Receive FIFO is not full. |
2 | RFE | R | 1h | Receive FIFO empty. 0h = Receive FIFO is not empty. 1h = Receive FIFO is empty. |
1 | TNF | R | 1h | Transmit FIFO not full 0h = Transmit FIFO is full. 1h = Transmit FIFO is not full. |
0 | TFE | R | 1h | Transmit FIFO empty. 0h = Transmit FIFO is not empty. 1h = Transmit FIFO is empty. |
RXDATA is shown in Figure 17-62 and described in Table 17-62.
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RXDATA Register
Reading this register returns value(s) of FIFO. If the FIFO is empty the last read value is returned.
Writing has not effect and is ignored.
When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R | 0h | Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer. 0h = Smallest value FFFFFFFFh = Highest possible value |
TXDATA is shown in Figure 17-63 and described in Table 17-63.
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TXDATA Register
Writing puts the data into the TX FIFO. Reading this register returns the last written value.
When PACKEN=0, only the
lower 16-bits of data written into the register is transferred to one 16-bits wide TX FIFO entry
When PACKEN=1, upper and lower 16-bits of 32-bit write data are transferred to two16-bits wide TX FIFO entry
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Transmit Data When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. 0h = Smallest value FFFFFFFFh = Highest possible value |
TEST0 is shown in Figure 17-64 and described in Table 17-64.
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Test 0 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DTB_MUX_SEL | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | DTB_MUX_SEL | R/W | 0h | This bit field is used to select DTB mux digital output signals. 0h = Disables DTB MUX 1h = Selects test group 1 2h = Selects test group 2 3h = Selects test group 3 4h = Selects test group 4 5h = Selects test group 5 6h = Selects test group 6 7h = Selects test group 7 8h = Selects test group 8 9h = Selects test group 9 |