SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
The AES accelerator must be enabled before being configured for use through the PWREN register (see peripheral power enable). The AES accelerator is located in power domain 1 (PD1) and as such is only available in RUN and SLEEP modes. If the AES accelerator is enabled by application software, entry into STOP or STANDBY low-power modes will force the AES accelerator to be disabled while the device is in STOP or STANDBY mode, and the AES accelerator register contents will be lost (including any key or state contents).
Data Sizes for Reading and Writing Keys and Data
The module allows 32-bit word or 8-bit byte access to all key and data registers (AESAKEY, AESADIN, AESAXDIN, AESAXIN, and AESADOUT). Word and byte access must not be mixed while reading from or writing into one of the registers. However, it is possible to write one of the registers using byte access and another using word access.
General Access Restrictions
While the AES accelerator is busy (AESBUSY bit is set in the AESASTAT register):
AESADIN, AESAXDIN, AESAXIN, and AESAKEY are write-only registers and always read as zero.
Writing data into AESADIN, AESAXDIN, or AESAXIN influences the content of the corresponding output data; for example, writing in[0] alters out[0], writing in[1] alters out[1], and so on. However, interleaved operation is possible; for example, first reading out[0] and then writing in[0], and continuing with reading out[1] and then writing in[1], and so on. This interleaved operation must be either byte or word access on in[x] and out[x].
Access Restriction With Block Cipher Modes Enabled
When automated block cipher modes are enabled (CMEN is set in AESACTL0) and a cipher block operation is being processed (BLKCNTx > 0), writes to the following bits are ignored, independent of the BUSY bit status: CMEN, CMx, KLx, OPx, and BLKCNTx. Writing to AESAKEY aborts the cipher block mode operation if BUSY = 1, and the complete module is reset (except for the IMASK registers, OPx, and KLx).