SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
The DAC supports programmable resolution setting and data format . The figures given in this section take DATA0 register as an example and describe the format in which CPU or DMA controller is expected to write data into DATA0 register for one data sample.
The CPU always writes only into DATA0 register. If FIFO is disabled then CPU can write into only byte-0 for 8-bit DAC resolution and lower half-word (bytes 0 and 1) for 12-bit DAC resolution. The upper half-word of DATA0 register is never written.
When the FIFO is enabled, the CPU can write up to 4 data samples into DATA0 register for 8-bit resolution or 12-bit resolution.
Figure 14-5 shows the data format in DATA0 register for 8-bit binary or two's complement data.