SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
The DSSM provides 4 interrupt sources which can be configured to source a CPU interrupt event. In order of decreasing interrupt priority, the CPU interrupt events from the DSSM are given in Table 28-341.
Index (IIDX) | Name | Description |
---|---|---|
0 | TXIFG | Indicates that the TX_DATA buffer in the DSSM has received data. |
1 | RXIFG | Indicates that the data in RX_DATA buffer in the DSSM was read. |
2 | PWRUPIFG | Indicates that the DEBUGSS was started due to a debug probe attaching to the device. |
3 | PWRDWNIFG | Indicates that the DEBUGSS was stopped due to a debug probe disconnecting from the device. |
The CPU interrupt event configuration is managed with the CPU_INT event management registers. See Section 7.2.5 for guidance on configuring the Event registers for CPU interrupts.