The ADC status register, STATUS,
contains two bits – REFBUFRDY and BUSY.
- REFBUFRDY is set when the ADC
receives the ready signal from the internal reference buffer (VREF/REFBUF)
after asserting the enable request
- BUSY equaling ‘1’ indicates that the ADC is busy performing a sample or
convert operation
- For single channel single conversion, it signals that a
trigger has been received and sample or conversion is ongoing. BUSY
will be cleared when the conversion completes
- For repeat single conversion, it signals that repeat single
operation has begun and has not ended. BUSY will be cleared when ENC
is written ‘0’ and the last conversion completes
- For sequence of channels conversion, it signals that the
sequence of channels conversion has started. BUSY will be cleared at
the end of the sequence
- For repeat
sequence of channels conversion, it signals the repeat
sequence is ongoing. BUSY will be cleared when ENC is written ‘0’
and the last conversion completes