The MSPM0 devices include a dedicated event manager peripheral, which extends the concept of the NVIC to allow digital events from a peripheral to be transferred to the CPU as interrupts, to the DMA as a trigger, or to another peripheral to trigger a hardware action. The event manager can also perform handshaking with the power management and clock unit (PMCU), to make sure that the necessary clock and power domain are present for triggered event actions to take place.

In the MSPM0 event manager, the peripheral that generates the event is known as a publisher, and the peripheral, DMA, or CPU that acts based on the publisher is known as the subscriber. The potential combinations of available publisher and subscriber are extremely flexible and can be used when migrating software to replace functionality previously handled by interrupt vectors and the CPU, to bypass the CPU entirely. For example, an I²C-to-UART bridge may previously have triggered a UART transmission upon receipt of an I²C STOP, using an ISR to set a flag, or load the UART TX buffer directly. With the MSPM0 Event handler, the I²C transaction complete event could trigger the DMA to load the UART TX buffer directly, and therefore eliminate the need for any action by the CPU.

To get more details on the use of the event handler in MSPM0, see the Events section of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual or the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual.