SLAU936 August   2024 TAS2120

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Quick Start Guide
    1. 2.1 TAS2120EVM Setup for Software Mode
    2. 2.2 TAS2120EVM Setup for Hardware Mode
  9. 3Hardware
    1. 3.1  AC-MB Settings
      1. 3.1.1 Audio Serial Interface Settings
      2. 3.1.2 USB Audio AC-MB Settings
      3. 3.1.3 External Audio AC-MB Settings
    2. 3.2  AC-MB Power Supply
    3. 3.3  Default Jumper Setting on TAS2120EVM
    4. 3.4  I2C Target Address Selection
    5. 3.5  IOVDD Power Supply Options
    6. 3.6  AVDD Power Supply Options
    7. 3.7  VBAT Power Supply Options
      1. 3.7.1 VBAT 3S EVM Hardware Configuration
    8. 3.8  IOVDD_BUFF Power Supply Options
    9. 3.9  Speaker Outputs
    10. 3.10 2-Channel Configuration
    11. 3.11 4-Wire Measurement of Load
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks

3.7.1 VBAT 3S EVM Hardware Configuration

This section shows how to set the EVM jumpers to evaluate TAS2120EVM in a 3S battery application for VBAT as depicted in Figure 1-3.

VBAT pin must still be connected to a power supply range from 3V up to 5V. VBAT_SNS cannot be used so VBAT_SNS must be shorted to GND. The internal boost is not used, so the SW pins are left floating and the inductor can be removed from the circuit.

3S battery supply range from VBAT pin level up to 14V is directly connected to PVDD node. The decoupling capacitors and GREG capacitor are still required.

  • VBAT pin 5V connection can be powered from VIN (J21) by setting J5 position to 2-3 (default).
  • VBAT_SNS pin connection must be left as default with J4 shorted across pins 2-3.
  • 3S VBAT supply must be connected to J13.