SLAZ742B July 2023 – December 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
ADC Module
Functional
ADC Output code jumps degrading DNL/INL specification
The ADC may have errors at a rate as high as 1 in 2M conversions in 12-bit mode.
When a conversion error occurs, it will be a significant random jump in the digital output
of the ADC without a corresponding change in the ADC input voltage. The magnitude of
this jump is larger near major transitions in the bit values of the ADC result (more bits
transitioning from 1->0, or 0->1), and largest around midscale (2048 or 0x800).
Depending on the application needs the best workaround may vary, but the following
workarounds in software are proposed. Selection of the best workaround is left to the
judgment of the system designer.
Workaround 1: Upon ADC result outside of application threshold (via ADC Window Comparator or
software thresholding), trigger or wait for another ADC result before making critical system
decisions
Workaround 2: During post-processing, discard ADC values which are sufficiently far from the median
or expected value. The expected value should be based on the average of real samples
taken in the system, and the threshold for rejection should be based on the magnitude of
the measured system noise.
Workaround 3: Use ADC sample averaging to minimize the effect of the results of any single incorrect
conversion.