SLLSEQ7E December   2015  – December 2019 TCAN330 , TCAN330G , TCAN332 , TCAN332G , TCAN334 , TCAN334G , TCAN337 , TCAN337G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
    8. 8.8 Typical Characteristics, TCAN330 Receiver
    9. 8.9 Typical Characteristics, TCAN330 Driver
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 TXD Dominant Timeout (TXD DTO)
      2. 10.3.2 RXD Dominant Timeout (RXD DTO)
      3. 10.3.3 Thermal Shutdown
      4. 10.3.4 Undervoltage Lockout and Unpowered Device
      5. 10.3.5 Fault Pin (TCAN337)
      6. 10.3.6 Floating Pins
      7. 10.3.7 CAN Bus Short Circuit Current Limiting
      8. 10.3.8 ESD Protection
      9. 10.3.9 Digital Inputs and Outputs
    4. 10.4 Device Functional Modes
      1. 10.4.1 CAN Bus States
      2. 10.4.2 Normal Mode
      3. 10.4.3 Silent Mode
      4. 10.4.4 Standby Mode with Wake
      5. 10.4.5 Bus Wake via RXD Request (BWRR) in Standby Mode
      6. 10.4.6 Shutdown Mode
      7. 10.4.7 Driver and Receiver Function Tables
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Bus Loading, Length and Number of Nodes
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 CAN Termination
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
      1. 11.3.1 ISO11898 Compliance of TCAN33x Family of 3.3-V CAN Transceivers Introduction
      2. 11.3.2 Differential Signal
      3. 11.3.3 Common-Mode Signal and EMC Performance
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

8.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant and dominant to recessive See Figure 23, S, STB and SHDN = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 100 135 ns
tPROP(LOOP) Total Loop delay in highly loaded network See Figure 23, S, STB and SHDN = 0 V, RL = 120 Ω, CL = 200 pF,
CL(RXD) = 15 pF 		120 180 ns
tBUS_SYM_2 2 Mbps transmitted recessive bit width See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF,
tBIT = 500 ns
TCAN330G, TCAN332G, TCAN334G and TCAN337G only		 435 530 ns
tREC_SYM_2 2 Mbps received recessive bit width 400 550 ns
ΔtSYM_2 2 Mbps receiver timing symmetry
(tREC_SYM_2 - tBUS_SYM_2)		 –65 40 ns
tBUS_SYM_5 5 Mbps transmitted recessive bit width See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF,
tBIT = 200 ns
TCAN330G, TCAN332G, TCAN334G and TCAN337G only		 155 210 ns
tREC_SYM_5 5 Mbps received recessive bit width 120 220 ns
ΔtSYM_5 5 Mbps receiver timing symmetry
(tREC_SYM_5 - tBUS_SYM_5)		 –45 15 ns
tMODE Mode change time See Figure 21 and Figure 22.
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF		 5 10 µs
tUV_RE-ENABLE Re-enable time after UV event Time for device to return to normal operation from UV(VCC) under voltage event 1000 µs
tWK_FILTER Bus time to meet Filtered Bus Requirements for Wake Up Request See Figure 33, Standby mode.
–12 V < VCM < 12 V 		0.5 4 µs
Driver Switching Characteristics
tpHR Propagation delay time, HIGH TXD to Driver Recessive See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF, 25 ns
tpLD Propagation delay time, LOW TXD to Driver Dominant 20
tsk(p) Pulse skew (|tpHR - tpLD|) 5
tr Differential output signal rise time 17
tf Differential output signal fall time 9
tTXD_DTO Driver dominant time out (1) See Figure 25,
RL = 60 Ω, CL = 100 pF		 1.2 2.6 3.8 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high RXD output See Figure 20, CL(RXD) = 15 pF CANL = 1.5 V, CANH = 3.5 V 62 ns
tpDL Propagation delay time, bus dominant input to RXD low output 56
tr Output signal rise time (RXD) 7
tf Output signal fall time (RXD) 6
tRXD_DTO Receiver dominant time out (2) See Figure 27, CL(RXD) = 15 pF 1.6 3 5 ms
(1) The TXD dominant time out (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than tTXD_DTO, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
(2) The RXD timeout (tRXD_DTO) disables the RXD output in the case that the bus has been dominant longer than tRXD_DTO, which releases RXD pin to the recessive state (high), thus preventing a dominant bus failure from permanently keeping the RXD pin low. The RXD pin will automatically resume normal operation once the bus has been returned to a recessive state. While this protects the protocol controller from a permanent dominant state, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on RXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tRXD_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / tRXD_DTO = 11 bits / 1.6 ms = 6.9 kbps.
TCAN330 TCAN332 TCAN334 TCAN337 TCAN330G TCAN332G TCAN334G TCAN337G TXD_DTO_and_FAULT_sllseq7.gifFigure 1. Example Timing Diagram for TXD DTO and FAULT Pin
TCAN330 TCAN332 TCAN334 TCAN337 TCAN330G TCAN332G TCAN334G TCAN337G RXD_DTO_and_FAULT_sllseq7.gifFigure 2. Example Timing Diagram for RXD DTO and FAULT Pin