SLLSER8J June   2017  – August 2024 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

8.3.3 Output Stage

The output stages of the UCC53x0 family feature a pull-up structure that delivers the highest peak-source current when it is most needed which is during the Miller plateau region of the power-switch turn-on transition (when the power-switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. Table 8-1 lists the typical internal resistance values of the pull-up and pull-down structure.

Table 8-1 UCC53x0 On-Resistance
DEVICE OPTION RNMOS ROH ROL RCLAMP UNIT
UCC5320SC and UCC5320EC 4.5 12 0.65 Not applicable Ω
UCC5310MC 4.5 12 1.3 1.3 Ω
UCC5390SC and UCC5390EC 0.76 12 0.13 Not applicable Ω
UCC5350MC 1.54 12 0.26 0.26 Ω
UCC5350SB 1.54 12 0.26 Not applicable Ω

The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device only. This parameter is only for the P-channel device, because the pull-up N-channel device is held in the OFF state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. Therefore, the effective resistance of the UCC53x0 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH parameter, which yields a faster turn-on. The turn-on-phase output resistance is the parallel combination ROH || RNMOS.

The pull-down structure in the UCC53x0 S and E versions is simply composed of an N-channel MOSFET. For the M version, an additional FET is connected in parallel with the pull-down structure when the CLAMP and OUT pins are connected to the gate of the IGBT or MOSFET. The output voltage swing between VCC2 and VEE2 provides rail-to-rail operation.

UCC5310 UCC5320 UCC5350 UCC5390 Output Stage—S Version Figure 8-6 Output Stage—S Version
UCC5310 UCC5320 UCC5350 UCC5390 Output Stage—E Version Figure 8-7 Output Stage—E Version
UCC5310 UCC5320 UCC5350 UCC5390 Output Stage—M Version Figure 8-8 Output Stage—M Version