7 Parameter Measurement Information

Figure 7-1 Common Mode Output Voltage Test Circuit

Figure 7-2 Propagation Delay Input to Output

Figure 7-3 Output Rise and Fall Times

Figure 7-4 Output Inter-Pair Skew

Figure 7-5 V_(pre) and V_(post) (test pattern is 1111111100000000 (8-1s, 8-0s))

Figure 7-6 Receive Side Performance Test Circuit

Figure 7-7 Transmit Side Performance Test Circuit

Figure 7-8 Equivalent Input Circuit

Figure 7-9 3-Level Input Biasing Network

Figure 7-10 Two – Wire Serial Interface Data Transfer

Figure 7-11 Two – Wire Serial Interface Timing Diagram