SLLSES6C February   2016  – December 2021 SN65DP141

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics, I2C Interface
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC and AC Independent Gain Control
      2. 8.3.2 Two-Wire Serial Interface and Control Logic
      3. 8.3.3 Bus Idle
      4. 8.3.4 Start Data Transfer
      5. 8.3.5 Stop Data Transfer
      6. 8.3.6 Data Transfer
      7. 8.3.7 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 TRACE and CABLE Equalization Modes
      2. 8.4.2 Control Modes
      3. 8.4.3 GPIO MODE
      4. 8.4.4 I2C Mode
    5. 8.5 Register Maps
      1. 8.5.1  Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
      2. 8.5.2  Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
      3. 8.5.3  Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
      4. 8.5.4  Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
      5. 8.5.5  Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
      6. 8.5.6  Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
      7. 8.5.7  Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
      8. 8.5.8  Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
      9. 8.5.9  Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
      10. 8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER CONSUMPTION
PDL Device Power dissipation VOD = Low, VCC = 3.3 V and all 4 channels active 450 625 mW
VOD = Low, VCC = 2.5 V and all 4 channels active 317 475 mW
PDH Device Power dissipation VOD = High, VCC = 3.3 V and all 4 channels active 697 925 mW
VOD = High, VCC = 2.5 V and all 4 channels active 485 675 mW
PDOFF Device power with all 4 channels switched off Refer to I2C section for device configuration 10 mW
CMOS DC SPECIFICATIONS
IIH High level input current VIN = 0.9 × VCC -40 17 40 µA
IIL Low level input current VIN = 0.1 × VCC -40 17 40 µA
CML INPUTS (IN[3:0]_P, IN[3:0]_N)
RIN Differential input resistance INx_P to INx_N 100 Ω
VIN Input linear dynamic range Gain = 0.5 1200 mVpp
VICM Input common mode voltage Internally biased VCC – 0.8 V
SCD11 Input differential to common mode conversion 100 MHz to 6 GHz -20 dB
SDD11 Differential input return loss 100 MHz to 6 GHz -15 dB
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
VOD Output linear dynamic range RL = 100 Ω, VOD = HIGH 1200 mVpp
RL = 100 Ω, VOD = LOW 600 mVpp
VOS Output offset voltage RL = 100 Ω, 0 V applied at inputs 10 mVpp
VOCM Output common mode voltage VCC – 0.4 V
VCM(RIP) Common mode output ripple K28.5 pattern at 12 Gbps on all 4 channels, No interconnect loss, VOD = HIGH 10 20 mVRMS
VOD(RIP) Differential path output ripple K28.5 pattern at 12 Gbps on all channels, No interconnect loss, VIN = 1200 mVpp. 20 mVpp
VOC(SS) Change in steady-state common mode output voltage between logic states ±10 mV