SLLSEY2G March   2017  – August 2021 ISOW7840 , ISOW7841 , ISOW7842 , ISOW7843 , ISOW7844

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—5-V Input, 5-V Output
    10. 7.10 Supply Current Characteristics—5-V Input, 5-V Output
    11. 7.11 Electrical Characteristics—3.3-V Input, 5-V Output
    12. 7.12 Supply Current Characteristics—3.3-V Input, 5-V Output
    13. 7.13 Electrical Characteristics—5-V Input, 3.3-V Output
    14. 7.14 Supply Current Characteristics—5-V Input, 3.3-V Output
    15. 7.15 Electrical Characteristics—3.3-V Input, 3.3-V Output
    16. 7.16 Supply Current Characteristics—3.3-V Input, 3.3-V Output
    17. 7.17 Switching Characteristics—5-V Input, 5-V Output
    18. 7.18 Switching Characteristics—3.3-V Input, 5-V Output
    19. 7.19 Switching Characteristics—5-V Input, 3.3-V Output
    20. 7.20 Switching Characteristics—3.3-V Input, 3.3-V Output
    21. 7.21 Insulation Characteristics Curves
    22. 7.22 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Power-Up and Power-Down Behavior
      3. 9.3.3 Current Limit, Thermal Overload Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
        1. 10.2.3.1 Insulation Lifetime
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Support Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air>8mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface>8mm
DTIDistance through the insulationMinimum internal gap (internal clearance – capacitive signal isolation)> 21µm
Minimum internal gap (internal clearance – transformer power isolation)>120
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 300 VRMSI-IV
Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE 0884-11:2017-01(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)1414VPK
VIOWMMaximum working isolation voltageAC voltage; Time dependent dielectric breakdown (TDDB) Test; See Figure 10-51000VRMS
DC voltage1414VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)		7071VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)		6250VPK
qpdApparent charge(4)Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s		≤ 5pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s		≤ 5
Method b1, at routine test (100% production) and preconditioning (type test),
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s		≤ 5
CIOBarrier capacitance, input to output(5)VIO = 0.4 × sin (2πft), f = 1 MHz~3.5pF
RIOInsulation resistance(5)VIO = 500 V,  TA = 25°C> 1012Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V,  TS = 150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISO(UL)Withstand isolation voltageVTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100% production)		5000VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.