SLLSFC5C November   2021  – January 2023 ISOUSB211

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply Options
      2. 8.3.2  Power Up
      3. 8.3.3  Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 8.3.4  Connect and Speed Detection
      5. 8.3.5  Disconnect Detection
      6. 8.3.6  Reset
      7. 8.3.7  LS/FS Message Traffic
      8. 8.3.8  HS Message Traffic
      9. 8.3.9  Equalization and Pre-emphasis
      10. 8.3.10 L2 Power Management State (Suspend) and Resume
      11. 8.3.11 L1 Power Management State (Sleep) and Resume
      12. 8.3.12 HS Test Mode Support
      13. 8.3.13 CDP Advertising
    4. 8.4 Device Functional Modes
  10. 9 Power Supply Recommendations
  11. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Isolated Host or Hub
      2. 10.1.2 Isolated Peripheral - Self-Powered
      3. 10.1.3 Isolated Peripheral - Bus-Powered
      4. 10.1.4 Application Curve
        1. 10.1.4.1 Insulation Lifetime
    2. 10.2 Meeting USB2.0 HS Eye-Diagram Specifications
    3. 10.3 Thermal Considerations
      1. 10.3.1 VBUS / V3P3V Power
      2. 10.3.2 VCCx / V1P8Vx Power
      3. 10.3.3 Example Configuration 1
      4. 10.3.4 Example Configuration 2
      5. 10.3.5 Example Configuration 3
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

5 Pin Configuration and Functions

GUID-20200818-CA0I-SDPH-FR7W-Z6MTWNZQ27QN-low.svg Figure 5-1 DP Package 28-Pin SSOP Top View
Table 5-1 Pin Functions—28 Pins
PIN I/O DESCRIPTION
NO. NAME
1 VBUS1 — Input Power Supply for Side 1. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply.
2 V3P3V1 — Power Supply for Side 1. If a 4.25 V to 5.5 V supply is connected to VBUS1 connect a bypass capacitor between V3P3V1 and GND1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply.
3 GND1 — Ground 1. Ground reference for Isolator Side 1.
4 V1P8V1 — Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC1 connect a bypass capacitor between V1P8V1 and GND1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply.
5 VCC1 — Input Power Supply for Side 1. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply.
6 V2OK O High level on this pin indicates that side 2 is powered up.
7 UD- I/O Upstream facing port D-.
8 UD+ I/O Upstream facing port D+.
9 EQ10 I Equalization setting for Side 1, LSB. Logic Input.
10 EQ11 I Equalization setting for Side 1, MSB. Logic Input.
11 V1P8V1 — Connect pin 11 to pin 4, with local bypass capacitors near pin 11.
12 GND1 — Ground 1. Ground reference for Isolator Side 1.
13 CDPENZ1 I Active low singal. Enables CDP advertising on UD+/UD- pins.
14 NC — Leave floating or connect to V3P3V1.
15 NC — Leave floating or connect to V3P3V2.
16 CDPENZ2 I Active low singal. Enables CDP advertising on DD+/DD- pins.
17 GND2 — Ground 2. Ground reference for Isolator Side 2.
18 V1P8V2 — Connect pin 18 to pin 25, with local bypass capacitors near pin 18.
19 EQ21 I Equalization setting for Side 2, MSB. Logic Input.
20 EQ20 I Equalization setting for Side 2, LSB. Logic Input.
21 DD+ I/O Downstream facing port D+.
22 DD- I/O Downstream facing port D-.
23 V1OK O High level on this pin indicates that side 1 is powered up.
24 VCC2 — Input Power Supply for Side 2. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply.
25 V1P8V2 — Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC2 connect a bypass capacitor between V1P8V2 and GND2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply.
26 GND2 — Ground 2. Ground reference for Isolator Side 2.
27 V3P3V2 — Power Supply for Side 2. If a 4.25 V to 5.5 V supply is connected to VBUS2 connect a bypass capacitor between V3P3V2 and GND1. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply.
28 VBUS2 — Input Power Supply for Side 2. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS2. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply.