SLLSFC5C November   2021  – January 2023 ISOUSB211

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply Options
      2. 8.3.2  Power Up
      3. 8.3.3  Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 8.3.4  Connect and Speed Detection
      5. 8.3.5  Disconnect Detection
      6. 8.3.6  Reset
      7. 8.3.7  LS/FS Message Traffic
      8. 8.3.8  HS Message Traffic
      9. 8.3.9  Equalization and Pre-emphasis
      10. 8.3.10 L2 Power Management State (Suspend) and Resume
      11. 8.3.11 L1 Power Management State (Sleep) and Resume
      12. 8.3.12 HS Test Mode Support
      13. 8.3.13 CDP Advertising
    4. 8.4 Device Functional Modes
  10. 9 Power Supply Recommendations
  11. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Isolated Host or Hub
      2. 10.1.2 Isolated Peripheral - Self-Powered
      3. 10.1.3 Isolated Peripheral - Bus-Powered
      4. 10.1.4 Application Curve
        1. 10.1.4.1 Insulation Lifetime
    2. 10.2 Meeting USB2.0 HS Eye-Diagram Specifications
    3. 10.3 Thermal Considerations
      1. 10.3.1 VBUS / V3P3V Power
      2. 10.3.2 VCCx / V1P8Vx Power
      3. 10.3.3 Example Configuration 1
      4. 10.3.4 Example Configuration 2
      5. 10.3.5 Example Configuration 3
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
DP-28
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >8 mm
CPG External Creepage(1) Side 1 to side 2 distance across package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 8000 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-us waveform per IEC 62368-1 8000 VPK
VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1 12800 VPK
qpd Apparent charge(4) Method a, After Input/Output safety test subgroup 2/3,Vini = VIOTM, tini = 60 s;Vpd(m) = 1.2 × VIORM, tm = 10 s ≤ 5 pC
Method a, After environmental tests subgroup 1,Vini = VIOTM, tini = 60 s;Vpd(m) = 1.6 × VIORM, tm = 10 s ≤ 5
Method b: At routine test (100% production) and preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)
 		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 pft), f = 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C > 1012 W
VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 5700 VRMS
(1) Care must be taken during board design so that the mounting pads of the isolator on the printed-circuit board (PCB) do not reduce creepage and clearance. Inserting grooves, ribs or both can help increase creepage distance on the PCB.
(2) ISOUSB211 is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.