SLLSFL3A April   2022  – May 2024 TUSB1004

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.1 x2 Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1004 I2C Address Options
      3. 7.5.3 TUSB1004 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1004 Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 8.2.2.2 USB CRX1/2 Receiver Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Full Adaptive Equalization
          3. 8.2.2.2.3 Fast Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Rx EQ Configuration in Pin-Strap Mode

The TUSB1004 configured in pin-strap mode uses the follow pins to control the EQ setting for each of its receivers: EQCFG pin, SSEQ[1:0] pins, CEQ[1:0] pins.

Table 7-5 Pin-strap: SSTX1 and SSTX2 Receiver EQ Configuration
SSTX Receiver SSEQ[1:0] pin level Gain at 5 GHz EQCFG pin level
SSTX1 SSEQ0 = "0"

3 dB

"1" or "R"
SSEQ0 = "R" 6 dB "1" or "R"
SSEQ0 = "F" 9 dB "1" or "R"
SSEQ0 = "1" 12 dB "1" or "R"
16 possible settings based on SSEQ0 and SSEQ1 Refer to Table 7-3. "0" or "F"
SSTX2 SSEQ1 = "0" 3 dB "1" or "R"
SSEQ1 = "R" 6 dB "1" or "R"
SSEQ1 = "F" 9 dB "1" or "R"
SSEQ1 = "1" 12 dB "1" or "R"
16 possible settings based on SSEQ0 and SSEQ1 Refer to Table 7-3. "0" or "F"

The following table describes receiver equalization controls for the receivers facing the USB connector.

Table 7-6 Pin Strap: CRX1 and CRX2 EQ Configuration with AEQ Disabled
CRX Receiver CEQ[1:0] pin level Gain at 5 GHz EQCFG pin level
CRX1 CEQ0 = "0" 3 dB "0" or "R"
CEQ0 = "R" 6 dB "0" or "R"
CEQ0 = "F" 9 dB "0" or "R"
CEQ0 = "1" 12 dB "0" or "R"
16 possible settings based on CEQ0 and CEQ1 Refer to Table 7-2. "F" or "1"
CRX2 CEQ1 = "0" 3 dB "0" or "R"
CEQ1 = "R" 6 dB "0" or "R"
CEQ1 = "F" 9 dB "0" or "R"
CEQ1 = "1" 12 dB "0" or "R"
16 possible settings based on CEQ0 and CEQ1 Refer to Table 7-2. "F" or "1"