SLLSFL3A April   2022  – May 2024 TUSB1004

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.1 x2 Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1004 I2C Address Options
      3. 7.5.3 TUSB1004 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1004 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 8.2.2.2 USB CRX1/2 Receiver Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Full Adaptive Equalization
          3. 8.2.2.2.3 Fast Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.3 USB 3.2 Power States

The TUSB1004 monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the state of the USB 3.1 interface. Depending on the state of the USB 3.2 interface, the TUSB1004 can be in one of four primary modes of operation when USB 3.1 is enabled: Disconnect, U2/U3, U1, and U0 (Active).

The Disconnect state is the state in which TUSB1004 has not detected far-end termination on both upstream facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of the four states. The TUSB1004 remains in this state until far-end receiver termination has been detected on both UFP (SSRX) and DFP (CTX). The TUSB1004 immediately exits this mode and enters U0 once far-end termination is detected.

Once in U0 state, the TUSB1004 will redrive all traffic received on the port in both directions. U0 is the highest power mode of all USB 3.2 power states. The TUSB1004 remains in U0 state until electrical idle occurs on both UFP and DFP. Upon detecting electrical idle, the TUSB1004 immediately transitions to U1.

The U1 state is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1004 UFP and DFP receiver termination remains enabled. The UFP and DFP transmitter DC common mode is maintained. The power consumption in U1 is similar to power consumption of U0.

Next to the disconnect state, the U2/U3 state is next lowest power state. While in this state, the TUSB1004 periodically performs far-end receiver detection. Anytime the far-end receiver termination is not detected on either UFP or DFP, the TUSB1004 leaves the U2/U3 state and transitions to the Disconnect state. It also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1004 immediately transitions to the U0 state. In U2/U3 state, the TUSB1004 receiver terminations remain enabled but the TX DC common mode voltage is not maintained.