SLLSFL3A April   2022  – May 2024 TUSB1004

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.1 x2 Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1004 I2C Address Options
      3. 7.5.3 TUSB1004 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1004 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 8.2.2.2 USB CRX1/2 Receiver Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Full Adaptive Equalization
          3. 8.2.2.2.3 Fast Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 USB Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB Gen 2 Differential Receiver (CRX1p/n, CRX2p/n, SSTX1p/n, SSTX2p/n)
V(RX-DIFF-PP) Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 1200 mVpp
V(RX-DC-CM) Common-mode voltage bias in the receiver (DC) 0 V
VRX_CM-INST Max Instantaneous RX DC common-mode voltage change under all operating conditions (OFF to ON, Disabled to USB, and so forth) Measured at non-device side of AC coupling capacitor with  200-kΩ load. –300   500 mV
R(RX-DIFF-DC) Differential input impedance (DC) Present after a GEN2 device is detected. 72 90 120 Ω
R(RX-CM-DC) Receiver DC common mode impedance Present after a GEN2 device is detected. 18 30 Ω
Z(RX-HIGH-IMP-DC-POS) Common-mode input impedance with termination disabled (DC) Present when no GEN2 device is detected on transmitter. Measured over the range of 0-500mV with respect to GND. 25 kΩ
V(SIGNAL-DET-DIFF-PP) Input differential peak-to-peak signal detect assert level At 10 Gbps, no input loss, PRBS7 pattern 75 mV
V(RX-IDLE-DET-DIFF-PP) Input differential peak-to-peak signal detect deassert Level At 10 Gbps, no input loss, PRBS7 pattern 55 mV
V(RX-LFPS-DET-DIFF-PP) Low frequency periodic signaling (LFPS) detect threshold Below the minimum is squelched 100 300 mV
V(RX-CM-AC-P) Peak RX AC common-mode voltage Measured at package pin 150 mV
C(RX) RX input capacitance to GND At 5 GHz; 1 pF
RL(RX-DIFF) Differential return Loss 50 MHz – 1.25 GHz at 85 Ω; –22 dB
5 GHz at 85 Ω; –20 dB
RL(RX-CM) Common-mode return loss 50 MHz – 5 GHz at 85 Ω; –12 dB
EQ_SSTX15 SSTX1->CTX1 Receiver equalization at 5 GHz SSEQ1_SEL = 15; Gain at 5GHz minus Gain at 10MHz; 13.6 dB
EQ_RX15 CRX1 -> SSRX1 Receiver equalization at 5 GHz CEQ1_SEL = 15; Gain at 5GHz minus Gain at 10MHz; 12.7 dB
CAC-USB1 Required external AC capacitor on SSTX1/2 75 265 nF
CAC-USB2 Optional external AC capacitor on CRX1 and CRX2. 297 363 nF
USB Gen 2 Differential Transmitter (CTX1p/n, CTX2p/n, SSRX1p/n, SSRX2p/n)
VTX(DIFF-PP) Transmitter dynamic differential voltage swing range. EQ15; VID = 1Vpp; LINR_L3 1200 mVpp
VTX(RCV-DETECT) Amount of voltage change allowed during receiver detection 600 mV
VTX-CM-INST-ONOFF Max Instantaneous TX DC common-mode voltage change under operating condition:  OFF to ON, ON to OFF, during Rx.Detect; Disconnect to U0, U2/U3 to Disconnect. Measured single-ended at non-device side of AC coupling capacitor with  200-kΩ load. –500   800 mV
VTX(CM-IDLE-DELTA) Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS –300 600 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0.5 0.76 1 V
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVpp
VTX(IDLE-DIFF-AC-PP) AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX(CM-DC-ACTIVE-IDLE-DELTA) Absolute DC common-mode voltage between U1 and U0 At package pin 200 mV
RTX(DIFF) Differential impedance of the driver 80 90 120 Ω
RTX(CM) Common-mode impedance of the driver Measured with respect to AC ground over
0–500 mV		 18 30 Ω
VSSRX-LIMITED-VODL0 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L0 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 750 mVpp
VSSRX-LIMITED-VODL1 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L1 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 900 mVpp
VSSRX-LIMITED-VODL2 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L2 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1000 mVpp
VSSRX-LIMITED-VODL3 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L3 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1100 mVpp
VSSRX-DE-RATIO0 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b00; USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-7 –1.8 dB
VSSRX-DE-RATIO1 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-7 –2.1 dB
VSSRX-DE-RATIO2 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-7 –3.2 dB
VSSRX-DE-RATIO3 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-7 –3.8 dB
VSSRX-PRESH-RATIO0 SSRX preshoot level when configured for limited redriver and preshoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b00;  USB_SSRX_VOD = 2'b00 (LINR_L3); Refer to Figure 6-6 1.6 dB
VSSRX-PRESH-RATIO1 SSRX preshoot level when configured for limited redriver and preshoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-6 2.1 dB
VSSRX-PRESH-RATIO2 SSRX preshoot level when configured for limited redriver and preshoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-6 2.5 dB
VSSRX-PRESH-RATIO3 SSRX preshoot level when configured for limited redriver and preshoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3);  Refer to Figure 6-6 3.0 dB
ITX(SHORT) TX short circuit current TX± shorted to GND 60 mA
CTX(PARASITIC) TX input capacitance for return loss At package pins, at 5 GHz 1.25 pF
RLTX(DIFF) Differential return loss 50 MHz – 1.25 GHz at 85 Ω –28 dB
RLTX(CM) Common-mode return loss 50 MHz – 5 GHz at 85 Ω –12 dB
CTX-AC(COUPLING) External required AC coupling capacitor 75 265 nF
AC Characteristics
Crosstalk_CRXTX Differential crosstalk between CTX1/2 and CRX1/2 signal pairs 85 Ω; At 5 GHz; SSEQ[1:0] = 0; CEQ[1:0] = 0;  –40 dB
CPLF-LINRL0 Low-frequency –1dB compression point at LINR_L0 setting.  20 MHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 750 mVpp
CPHF-LINRL0 High-frequency –1dB compression point at LINR_L0 setting.   5 GHz clock pattern;  VID is 200mV to 1200mV in 10mV steps; 650 mVpp
CPLF-LINRL1 Low-frequency –1dB compression point at LINR_L1 setting.   20 MHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 850 mVpp
CPHF-LINRL1 High-frequency –1dB compression point at LINR_L1 setting.   5 GHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 750 mVpp
CPLF-LINRL2 Low-frequency –1dB compression point at LINR_L2 setting.   20 MHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 950 mVpp
CPHF-LINRL2 High-frequency –1dB compression point at LINR_L2 setting.   5 GHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 850 mVpp
CPLF-LINRL3 Low-frequency –1dB compression point at LINR_L3 setting.   20 MHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 1050 mVpp
CPHF-LINRL3 High-frequency –1dB compression point at LINR_L3 setting.   5 GHz clock pattern; VID is 200mV to 1200mV in 10mV steps; 900 mVpp
fLF Low frequency cutoff 200 mVPP< VID < 1200 mVPP 20 50 kHz
tTX_DJ_SSTX2-CTX2 TX output deterministic residual jitter SSTX2-> CTX2. Optimal EQ setting; 12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 10 Gbps .05 UI
tTX_DJ_SSTX1-CTX1 TX output deterministic residual jitter SSTX1-> CTX1. Optimal EQ setting; 12-in prechannel (SDD21 = -11.2dB); 1.6-in post channel (SDD21 = -1.8dB); PRBS7; 10 Gbps .05 UI