SLOS930C November   2015  – October 2024 THS4541-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 6.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 6.7 Typical Characteristics: 5-V Single Supply
    8. 6.8 Typical Characteristics: 3-V Single Supply
    9. 6.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Frequency-Response Shape Factors
    3. 7.3 I/O Headroom Considerations
    4. 7.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 7.5 Noise Analysis
    6. 7.6 Factors Influencing Harmonic Distortion
    7. 7.7 Driving Capacitive Loads
    8. 7.8 Thermal Analysis
  9. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin ( PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 8.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 8.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 8.4.2 Differential-Input to Differential-Output Operation
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Designing Attenuators
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Interfacing to High-Performance ADCs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

I/O Headroom Considerations

The starting point for most designs is usually to assign an output common-mode voltage. For ac-coupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing around the centered Vocm. For dc-coupled designs, set this voltage with consideration for the required minimum headroom to the supplies shown in the specifications for the Vocm control. From the target output Vocm, the next step is to verify that the desired output differential VPP stays within the supplies. For any desired differential Vopp, check that the absolute maximum output pin swings with Equation 2 and Equation 3, and confirm the differential Vopp are within the supply rails for this rail-to-rail (RR) output device.

Equation 2. THS4541-Q1
Equation 3. THS4541-Q1

For instance, driving the ADC3223 with a 0.95 Vcm control using a single 3.3-V supply, the maximum output swing is set by the negative-going signal from 0.95 Vcm to +0.2 V above ground. This 0.75-V, single-sided swing becomes an available 4 × 0.75 V = 3 VPP differential around the nominal 0.95 Vcm output common mode. On the high side, the maximum output is 0.95 + 0.75 = 1.7 V. This result is well within the allowed maximum of 3.3 V – 0.2 V = 3.1 V. This 3 VPP is also well beyond the maximum required 2-VPP full-scale differential input for this ADC. However, having this extra swing range is useful if an interstage filter to the ADC adds insertion loss.

With the output headrooms confirmed, the input junctions must also stay within the operating range. The input range extends to the negative supply voltage (over the full temperature range); therefore, input range limitations usually appear only approaching the positive supply, where a maximum 1.3-V headroom is required over the full temperature range.

The input pins operate at voltages set by the external circuit design, the required output Vocm, and the input signal characteristics. For differential-to-differential designs where the input Vicm voltage does not move with the input signal, there are two configurations to consider:

  • AC-coupled, differential-input designs have a Vicm equal to the output Vocm. The input Vicm requires approximately a 1.3-V headroom to the positive supply; therefore, the maximum Vocm to that value reduces from the Vocm positive headroom requirement of 1.2 V to the 1.3 V required on the input pins. The lower limit on the output Vocm is approximately 0.95 V to the negative supply over the full temperature range, and well within the 0-V minimum headroom on the input Vicm.
  • DC-coupled, differential-input designs, check the voltage divider from the source Vcm to the THS4541-Q1 Vocm setting to confirm the resulting voltage divider solves to an input Vicm within the allowed range. If the source Vcm can vary over some voltage range, this result must be validated over that range.

For single-ended input to differential output designs, there is a dc Vicm voltage set by the external configuration with a small-signal related swing around that. The two conditions to consider are:

  • AC-coupled, single-ended input to differential designs place an average input Vicm equal to the output Vocm voltage with an ac-coupled swing around that Vocm following the input voltage.
  • DC-coupled, single-ended input to differential designs get a nominal input Vicm set by the source-signal common mode and the output Vocm setting with a small, signal-related swing around the dc Vicm level set by the voltage divider.

One method of deriving the voltage range for Vicm for any single-ended input to differential output design is to determine the voltage swing on the nonsignal-input side of the FDA outputs and simply take the respective divider back to the input pin to ground or the dc reference used on that side. An example analysis is shown in Figure 7-8, where the circuit of Figure 7-1 is simplified to show just a Thevenized source impedance.

THS4541-Q1 Input Swing Analysis
                                                  Circuit From Figure 7-1 With Thevenized SourceFigure 7-8 Input Swing Analysis Circuit From Figure 7-1 With Thevenized Source

For this ac-coupled input analysis, the nominal dc input Vicm is simply the output Vocm (2.5 V in this example design). Then, considering the lower side of the feedback networks, any desired maximum output differential VPP generates a known ac VPP at the junction of Rg2 and Rf2. For instance, if the design intends a maximum 4-VPP differential output, each FDA output pin is ±1 V around the Vocm (= 2.5 V), and then back to the Vicm, which produces a ±1 V × 221 / (221 + 402) = ±0.355 V around the dc setting of Vocm. This simple approach to assessing the input Vicm range for a single-ended to differential design can be applied to any design using an FDA by reducing the input side circuits to a divider to either the signal source and ground or voltage reference on the nonsignal input side.