SLUAA61B September   2022  – November 2022 UCC27282-Q1 , UCC27284-Q1

 

  1. 1Functional Safety FIT Rate, FMD and Pin FMA
    1. 1.1 Overview
    2. 1.2 Functional Safety Failure In Time (FIT) Rates
      1. 1.2.1 SOIC Package
        1. 1.2.1.1 Failure Mode Distribution (FMD)
      2. 1.2.2 VSON Package
        1. 1.2.2.1 Failure Mode Distribution (FMD)
    3. 1.3 Pin Failure Mode Analysis (Pin FMA)
      1. 1.3.1 SOIC Package
      2. 1.3.2 VSON Package
  2. 2Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the UCC27282-Q1 (SOIC and VSON package). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 1-8 through Table 1-15 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 1-7.

Table 1-7 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • SOIC :Pin#1-4, Short to VDD is considered.
  • SOIC :Pin#5-6. Short to 5v such as MCU or controller I/O supply is considered.
  • SOIC :VSS is assumed to be a ground plane.
  • VSON :Pin#1-5 and 10, Short to VDD is considered.
  • VSON :Pin#6-8. Short to 5v such as MCU or controller I/O supply is considered.
  • VSON :VSS is assumed to be a ground plane.