SLUAA61B September   2022  – November 2022 UCC27282-Q1 , UCC27284-Q1

 

  1. 1Functional Safety FIT Rate, FMD and Pin FMA
    1. 1.1 Overview
    2. 1.2 Functional Safety Failure In Time (FIT) Rates
      1. 1.2.1 SOIC Package
        1. 1.2.1.1 Failure Mode Distribution (FMD)
      2. 1.2.2 VSON Package
        1. 1.2.2.1 Failure Mode Distribution (FMD)
    3. 1.3 Pin Failure Mode Analysis (Pin FMA)
      1. 1.3.1 SOIC Package
      2. 1.3.2 VSON Package
  2. 2Revision History

VSON Package

Figure 1-4 shows the UCC27282-Q1 pin diagram for the VSON package. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the UCC27282-Q1 data sheet.

GUID-A654F79C-2EEB-4F94-8123-671E154D5AC3-low.gifFigure 1-4 Pin Diagram (VSON Package)
Table 1-12 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VDD1LO will remain low. HO will remain low.B
NC2No effectD
HB3Device may be damaged with unknown LO/HO stateA
HO4Device may be damaged with unknown LO/HO stateA
HS5Device may be damaged with unknown LO/HO stateA
EN6LO will remain low. HO will remain low.B
HI7HO will be in a low stateB
LI8LO will be a low stateB
VSS9No effectD
LO10Device may be damaged with unknown LO/HO stateA
Table 1-13 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VDD 1 LO will remain low. HO will remain low. B
NC 2 No effect D
HB 3 HO will be pulled to HS potential B
HO 4 HO terminal not connected to the system D
HS 5 HO will be pulled to HB potential B
EN 6 LO will remain low. HO will remain low. B
HI 7 HO will be in a low state B
LI 8 LO will be in a low state B
VSS 9 HO will be in a low state LO will be pulled to VDD B
LO 10 LO terminal not connected to the system D
Table 1-14 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted to (PIN#+1)Description of Potential Failure Effect(s)Failure Effect Class
VDD1NCNo effectD
NC2HBNo effectD
HB3HODevice may be damaged with unknown HO stateA
HO4HSDevice may be damaged with unknown LO/HO stateA
HS5N/A--
EN6HILO/HO will follow the logic truth table per datasheet with EN in the same logic state as HIB
HI7LIHO/LO will be in a low stateB
LI8VSSLO will be a low stateB
VSS9LODevice may be damaged with unknown LO/HO stateA
LO10N/A--
Table 1-15 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VDD1No effectD
NC2No effectD
HB3Device may be damaged with unknown LO/HO stateA
HO4Device may be damaged with unknown LO/HO stateA
HS5Device may be damaged with unknown LO/HO stateA
EN6Short to 5V (I.E Power supply of the Microcontroller). LO/HO will follow the logic truth table per datasheet with EN stuck in a high state.B
HI7Short to 5V (I.E Power supply of the Microcontroller) LO/HO will follow the interlock truth table depending on LI/HIB
LI8Short to 5V (I.E Power supply of the Microcontroller) LO/HO will follow the interlock truth table depending on LI/HIB
VSS9HO will be in a low state LO will be pulled to VDDB
LO10Device may be damaged with unknown LO/HO stateA