SLUAAC0 September   2021 TPS92519-Q1 , TPS92520-Q1

 

  1.   Trademarks
  2. 1Introduction to Paralleling Current Sources
    1. 1.1 TPS92520-Q1
    2. 1.2 TPS92520-Q1 Design Considerations
      1. 1.2.1 Example Setup of Parallel Channels Generating 2-A Output Using TPS92520EVM-133 Board and GUI
    3. 1.3 TPS92519-Q1
    4. 1.4 TPS92519-Q1 Design Considerations
  3. 2Summary

1.4 TPS92519-Q1 Design Considerations

There are several design considerations that need to be addressed when paralleling the two channels of the TPS92519-Q1.

The COMPx pins for each channel need to be connected together with apposing diodes. See Figure 1-14. The two channels are independent, but in order for both control loops to engage the fault detection properly, then the diodes need to be placed between COMP1 and COMP2. The channels must have the channel currents controlled symmetrically, which means attaching IADJ1 and IADJ2 together. PWM control can be performed independently or synchronized between both channels.

Figure 1-14 TPS92519-Q1 Connections Needed to Support Parallel Channel Operation

The TPS92519EVM-169 needs to be modified to include the two diodes. See Figure 1-15. IADJ1 and IADJ2 are connected together and PWM1 and PWM2 are also connected together (PWMx test points inverter UDIMx signals). LED1+ and LED2+ test points need to be connected together and routed to the load (most cases are LEDs) along with the GND connections. The power supply, which was set to 48 V, is connected to either VIN2 or VIN1 (they are attached together on the TPS92519EVM-169 via R20 and the GND needs to be connected between the DC power supply and the EVM). A separate 5-V supply needs to be connected to the 5-V test point and GND test point on the TPS92519EVM-169.

Figure 1-15 Connecting TPS92519EVM-169 for Parallel Operation

Figure 1-16 illustrates the start-up of the parallel channels to achieve 4 A of drive current. VIADJ is set to 2.4 V on both channels of the EVM.

Figure 1-16 Parallel Channels Start-up Using Modified TPS92519EVM-1

Figure 1-17 demonstrates PWM control of the two parallel channels using PWM1 and PWM2 test points on the TPS92519EVM-169.

Figure 1-17 Parallel Channels Controlled by PWM Dimming Using Modified TPS92519EVM-169

Figure 1-18 illustrates the FLT flag being triggered when a short is applied to the parallel channels using the modified TPS92519EVM-169. FLT1 and FLT2 test points are tied together on TPS92519EVM-169.

Figure 1-18 Parallel Channels Exposed to Short Circuit Condition Using Modified TPS92519EVM-169

Figure 1-19 illustrates the FLT flag being triggered when modified TPS92519EVM-169 is exposed to an open condition.

Figure 1-19 Parallel Channels Exposed to Open Circuit Condition Using Modified TPS92519EVM-169