SLUAAC0 September   2021 TPS92519-Q1 , TPS92520-Q1

 

  1.   Trademarks
  2. 1Introduction to Paralleling Current Sources
    1. 1.1 TPS92520-Q1
    2. 1.2 TPS92520-Q1 Design Considerations
      1. 1.2.1 Example Setup of Parallel Channels Generating 2-A Output Using TPS92520EVM-133 Board and GUI
    3. 1.3 TPS92519-Q1
    4. 1.4 TPS92519-Q1 Design Considerations
  3. 2Summary

Example Setup of Parallel Channels Generating 2-A Output Using TPS92520EVM-133 Board and GUI

Connect the LEDMCUEVM-132 to the TPS92520EVM-133, and connect the USB cable from the computer to the LEDMCUEVM-132. See instructions for GUI installation and operation that are in the TPS92520EVM-133 User’s Guide and the LEDMCUEVM-133 User’s Guide.

Start by selecting the En 520 No WD button to disable the watchdog timer (CMWEN bit in SYSCFG1 register). Before turning on the channels, use the GUI to set the channels to the desired set points for IADJ, TON, and so forth. In this example, Analog Current is set to 600 decimal, which is approximately 1 A for each channel. Both use the default On Time of 7 decimal which is approximately 440 kHz. See Figure 1-8.

GUID-20201029-CA0I-6FSB-FRG5-7CRTNKDGVQDC-low.gif Figure 1-8 GUI After En 520 No WD Button is Selected, Which Disabled the Watch Dog Timer
Then, use the SPI command window to do a single write to the SYSCFG1 register (0x00h), such that the CH1EN, CH2EN, and PWMPH bits are high. In this example, we write 0x45h to register address 0x00h (SYSCFG1). See Figure 1-9.

GUID-20201029-CA0I-M1LM-PPWN-5CJNQX3NDPJW-low.gifFigure 1-9 Using GUI to Write 0x45h to SYSCFG1 Register at Address 0x00h

Channels 1 and 2 will then synchronously start-up and ramp up to 2 A at the outputs that are tied together. See Figure 1-10.

GUID-20201029-CA0I-TXS1-0SPM-MS6DBRTJT2JK-low.gif
CH1-SW1 voltage, CH2=SW2 voltage, CH3-VLED voltage, and CH4 is ILED current.
Figure 1-10 Start-up of Parallel Connections With Synchronized Start-up

Internal PWM dimming can be used at this point because the PWMPH bit is set high (PWM phase between channels is 0). We can see each channel has different duty cycles setting. See Figure 1-11 for GUI setting and see Figure 1-12 for oscope screen shot of two channels on at different duty cycles.

GUID-20201029-CA0I-ZFFL-TXTB-GV3NGBFDTDCH-low.gifFigure 1-11 Parallel Channels Using Internal PWM Settings Using the GUI
GUID-20201029-CA0I-00VP-BZX1-6DWX1CQ09DHZ-low.gif
CH1-SW1 voltage, CH2=SW2 voltage, CH3-VLED voltage, and CH4 is ILED current.
Figure 1-12 Parallel Channels With Different PWM Duty Cycles for Each Channel